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Is it bad if I connect the A_VDD and D_VDD Pins together if I want to use the same voltage? Or maybe I should ask: Why can I hook up different voltages other than galvanic decoupling? This is the IC I am talking about: AD7792 I am trying to measure Thermocouples.

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    \$\begingroup\$ Usually the A_VDD will be a precision reference for the analog chip, so this depends on what the D_VDD pin has on it, how noisy/dirty it is, and what your tolerances are for accuracy. \$\endgroup\$ – Ron Beyer Jun 27 '19 at 21:28
  • \$\begingroup\$ That chip has a separate reference, which is not uncommon for precision ADCs. \$\endgroup\$ – TimWescott Jun 27 '19 at 22:06
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Analog circuits are sensitive to variations and noise on their supply pins. In general, you connect A_VDD (and A_GND, if there is one) to a quiet supply, while D_VDD (and D_GND) can be connected to something dirtier.

It should be in the data sheet. Either connect A_VDD to a filtered version of D_VDD, derive A_VDD separately with its own dedicated regulator, or connect them together and accept that your ADC readings will be noisier than the datasheet specifies.

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First you should define your measurement accuracy specs and error budget then determine how much is acceptable for signal noise ground shift noise and supply differential noise.

When you have a fine resolution ADC, why waste SNR?

It has only 85 nV RMS noise.

Sharing DVdd which may degrade AVdd even when there is 100dB CMRR at 60Hz, it declines 20 dB per decade.

Filter the offending sources of digital noise currents then protect sensitive ground, Vref and signal currents.

When aVdd and dVdd are shared each with identical low ESR caps will there be circulating currents on impulse logic loads that might be a hundred or a thousand times bigger than the average current.

Meanwhile ripple on Vdd can be suppressed 20dB per decade from the equivalent load resistance, but the avg current * crest factor * cap ESR can still create errors on the Vref or ground return used for ADC and result in more missing codes during the successive approximation after the sample is taken.

Although this IC has some extra benefits of digital filtering, it is still prone to noise at integer multiples of the modulator sampling frequency up to 10kHz, so RF beads do not help.

This means the signal noise is sensitive to harmonics up to 10kHz but the supply and ground depends on the location of your excellent LDO where the ground planes should meet.

See here for an example where the supply is from USB.

USB shield for analog and digital ground?

enter image description here It is wise to isolate both the Vdd and Vss to prevent sharing currents even if they are ideally filtered from the same sources. This requires an understanding of ripple spectrum, split ground planes joined close to the regulator source and use recommended decoupling caps.

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  • \$\begingroup\$ Thanks for the advice regarding the filtering and the groundplanes. I learned something new here, though It was a bit hard to understand to be honest, as most of the stuff is new to me (especially the shortages). I am not entirely sure what your answer means regarding my original question; does it mean (correct me if I am wrong): I can connect A_VDD and D_VDD but I should decouple them as best as I can using capacitors and remove digital noise using a good layout. \$\endgroup\$ – RIJIK Jun 28 '19 at 21:45
  • \$\begingroup\$ Yes and sometimes this means using a a simulator to determine the attenuation in dB from crosstalk but keeping that path of least impedance away from each load to they source and return to the regulator without shared paths of circulating currents. 24bit sigma Delta is extremely low levels of noise per bit. But you can do a noise margin budget and see what you can afford to lose. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 '19 at 22:01
  • \$\begingroup\$ Layouts can be modelled by RLC networks with decoupling caps as RC networks. My first ADC hybrid from BB had these, I followed the rules and it still had missing codes. I later replaced the Mil-std 883 part with a industrial version and problem disappeared, so I concluded they had ground shift internally between TTL and Analog Vref so codes were missing going from ...111xxxx to ...1000xxx skipping due to noise on Vref ground. it was made by Burr Brown who is now owned by TI \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 '19 at 22:02

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