How do parallel resistors and capacitors reduces frequency peaking in opamps?

Question

I'm trying to understand a schematic from the front end of an analog discovery scope. It uses an AD8066 opamp, and has a resistor and capacitor in parallel on the inverting and non-inverting terminals.

These are supposed to reduce the gain spikes at increased frequencies at unity gain.

We can see here at gain=1, the higher frequencies start to spike:

Here is the part of the schematic that says the resistors and caps help reduce this. (5k and 100pf on +, and 10K 150pf on -):

I'm just trying to understand the theory on how it works, and how the values of the resistors and capacitors are chosen.

Answer 1

Reason for C15

Without C15, parasitic input capacitance on pin 6 to ground would causes a peak in the amplifier response because the negative feedback at high frequencies gets less and therefore the resulting gain gets higher. Consider this: -

In effect the impedance "R2" is lowered by parasitic capacitive reactance so you get more gain at higher frequencies. You also get more noise (it's called noise gain) so C15 reduces this too.

Reason for C20

Parasitic capacitance to ground on pin 5 will attenuate the input signal passing through R20 so, C20 is there to counter that effect.

Answer 2

Final Edit:

The differential input impedance is 1000 GΩ//4.5 pF for the differential mode (DM) input and 2.1pF for the common mode (CM) capacitance. See datasheet Fig 42 for comparison.

This network is called a "LEAD:LAG NETWORK" not just for phase margin but here to flatten the closed loop 1000 GOhm input impedance transfer function due to Cdm:Ccm peaking factors.

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I added this capacitance to an ideal Op AMP yet with a GBW of 145 MHz as I chose in the Falstad Sim.

Let’s plot the model response then compare the datasheet's Op Amp G=+1 frequency response to see how that might flatten the response.

Now the User Manual shows the resulting Bode Plot below.

The goal for this compensation was not to flatten the 80 MHz peaks since this frequency is above the Nyquist limit but rather to reduce the error at 10MHz down to 0.5dB which is 0 dB on better instruments.

The design criteria were probably defined by the designer to create a small boost starting with by 150/100pF=1.5:1 ratio but then shunted by the DM and CM capacitance ratios of 4.5pF/2.1pF of the FET inputs. Also using the large resistor values requires smaller capacitance values so as not to impact maximum square swing active current limiting at 170V/ns.

The Analog Discovery manual shows the results below with +0.1dB/-0.3dB passband ripple for high gain and +0/-0.5dB @ 10MHz for low gain.