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I've seen a number of PCBs, largely high speed and RF boards, that have exposed copper, either at the perimeter of the entire board, or in various sections, often with stitching vias.

I've never fully understood the purpose of these. Some explanations I've heard called them "ESD Rings" used for handling the board, but that makes less sense to me when there are a lot of individual perimeters, specifically ones more inboard like in the image below. Are these just the top ground plane exposed? If so, what's the point of exposing it? I don't see how it would make a difference from an EMI perspective whether said ground pours are exposed or not.

I've also heard, and more or less accept that for an outer perimeter plated ring of this kind, it's often connected to GND and then used to connect via mounting hardware to an enclosure.

Thanks!

enter image description here

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They are called via fences, they are placed on the outside of the board to "fence in RF", they do this by creating a barrier smaller than the wavelength that needs to be shielded. At very high frequencies, the area between planes can function as a waveguide/antenna and high frequencies can move between planes and out of the edge of the PCB.

In addition to this the planes on the top layer can be plated to accept EMI gaskets/shields.

enter image description here Source: https://sc01.alicdn.com/kf/HTB1uZSNRXXXXXahXpXXq6xXFXXXd/Photo-chemical-etching-RFI-EMI-shielding-box.jpg

Are these just the top ground plane exposed? If so, what's the point of exposing it?

The vias most likely connect to the ground plane and the trace/plane on the top layer, but doesn't have to be. The point of exposing it is to make it conductive and continuous. The layer is then plated with a surface finish that is low impedance/resistance metal like ENIG (with gold). This allows for the high frequency currents to be shorted to the ground plane with an EMI gasket (conductive foam or deform-able metal mesh) and return back to the source. Without the conductive layer on the top of the PCB, RF could potentially leak underneath the RF shield.

Many of the chips are generating RF on the board pictured above, to prevent cross talk and leakage, the EMI shield prevents RF from moving to other areas of the design, or outside of the board (entities like the FCC regulate how much devices can radiate radio frequencies). This is why the shield also partitions different sections of the PCB design.

Here is the distance charge for via fencing, if you wanted to see what frequencies they were trying to shield on the board above, you could measure between vias to find the cutoff frequency.

enter image description here
Source: https://www.edn.com/Pdf/ViewPdf?contentItemId=4406491

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  • \$\begingroup\$ Since this board uses so many 0.1" holes, do you think any of your incompatible shields would work for this design? I don't but logically they are for individual shields with large holes not for tuning as your examples are but for mounting outside the Faraday cage. so -1 for inaccurate shield examples. and technical RF substance why they are designed this way with and without microvias . even though it was not requested. It is still relevant \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 at 19:24
  • \$\begingroup\$ Incompatible shields? I was showing an example of a RF shield. I couldn't find a picture of the exact EMI shield that goes on this board, so I apologize. I found the next best thing, I was also a bit disappointed that there are not many pic's of shields with gaskets that are readily searchable. \$\endgroup\$ – Voltage Spike Jun 28 at 19:30
  • \$\begingroup\$ If you find one and explain a bit if the logic RF isolation I’ll definitely +1 \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 at 19:34
  • \$\begingroup\$ I'm not sure I follow the reason for being exposed versus covered in soldermask. Wouldn't the shielding be maintained if the copper layout was the same but covered? It's still conductive and would respond accordingly to EMI?Or is the point here specifically to use the conductive exposed grids to mate with the enclosure? \$\endgroup\$ – Kirill Safin Jun 28 at 19:38
  • \$\begingroup\$ Yes conductive grids to a Faraday shield for each module isolated from each other by walls or cavities. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 at 19:50
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There will be shielding added from above and attached to the PCB by screws (therefore the holes).
The shielding will not only shield the circuit from outside world but also subcircuits from each other.

Here is an example of such a shielding: enter image description here
image from http://tennvac.com/custom-shielding-solutions

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Answer: The mounting holes are a clear contact area for braided contact to a cover.

https://images.app.goo.gl/usAPvRQmVPCfHtQu9

You won’t find any online because these are all custom designs. The above is just a simple rectangular shape.

When you mix logic speeds and RF frequencies which both overlap here in this design up to 6 GHz range for these types, you need a good common ground with many layers yet isolate the logic impulse currents from conducting through the RF grounds.

So you will see microvias every \$\lambda/20\$ for the highest frequency of interest, to reduce the loop crossectional area of these logic current spikes (CMOS FETs have capacitance when switched).

The surface is likely immersion gold-plated copper to buried layers to reduce oxidation and prevent irregular thickness solder level plating that affects impedance of transmission lines.

You will not see microvias for all the linear RF stuff because their ground plane is isolated from logic ground plane. and they are only connected near the RF ports. This minimizes the crosstalk of conducted and radiate ground currents between logic and RF.

The wide boundary around each zone is like the Mexican-US border. It sinks stray radiation fields, reduces crosstalk, but it doesn't stop migration of current or voltage fields it all together. It is coplanar after all and stray coupling is always reduced with a ground track in between. But the digital side is also analog with edge jitter and internal processes that are still sensitive to adjacent module crosstalk.

It is common for Faraday shields to be soldered on top when needed to further reduce crosstalk using reflow.

If you've seen a number of these boards without shields, then they did a pretty darn good layout design. Nortel and others also did some of these designs without shields up to 1 Gbit/s with very balanced differential microstrips (also bankrupt). I have some pre-Y2K designs we did for 1 GHz ISM band for the AMR market with in-house tin plated brass boxes etched by local PCB shops.

Unfortunately, this company went bankrupt. It had over 130 patents and many roots like HP microwave and a dozen others all experts in mobile wireless technology. Intel bought all the patents.

Enter image description here

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  • 2
    \$\begingroup\$ @W5VO if all you do is manage flags and delete content make false assumptions and unilaterally delete comments, why not make improvements to the site by encouraging cordial communication and positive feedback in the social sense not a control system sense that that is unstable and unprofessional. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 28 at 21:42
  • \$\begingroup\$ "The wide boundary around each zone is like the Mexican-US border." ...In what ways? Heck, in ANY way? Other than as an incredibly poor and weirdly-specific analogy that's likely to be unhelpful to readers outside the US, I mean. (Or, if that's too subtle: That nonsense statement has no place in this answer.) \$\endgroup\$ – FeRD Oct 23 at 22:14
  • \$\begingroup\$ @FeRD sorry to go over your head with some humor and low inductance guards ( with machine guns on Mex side) \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Oct 23 at 22:19

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