The video processor (VDP) has 6*Fsc (21,47727 MHz) clock inputs, pins XTAL1 and XTAL2, which is inversion of XTAL1. Present circuit is built using quartz oscillator of above mentioned frequency, and 74HCU04 - and this circuit functions very well, outputting CMOS levels @ supply of 5V.
I am building encoder for S-video/composite, and it needs frequency of 4*Fsc (14.31818 MHz). Making another clocking circuit at this frequency introduces the problem of synchronizing VDP frequency and encoder's frequency to eliminate dot crawl and other artifacts. The best way to proceed must be obtaining 4*Fsc from the same master VDP generator.
- if propagation delay through inverters/gates is comparable to 1/2 of the frequency half cycle, they introduce glitches;
- while they keep overall frequency, two adjacent pulses' rising edges are not exactly at the distance of /1.5 of the master clock - and no documents state this, they state that their output is not 50/50 duty cycle, but not that their operation is not exactly /1.5 at the micro-scale. My encoder's datasheet states "The duty cycle of this input clock is not critical, but a fasted-edged clock should be used to prevent excessive jitter in the timing", and I am afraid 15 nanoseconds of the clock spread (@ 69 ns for whole clock period) may cause encoding problems, and thus deteriorate the output picture on the display device.
The part of the circuits I referred to, performing /3 clock division, seem to form very well timed rising edges in respect to adjacent output clocks, and I am looking forward for using it. But for this I need master clock to be twice than current - 42.95454 MHz. Then I will divide this clock by 2 to feed the VDP, and by 3 to feed the encoder.
The fundamental problems I am facing are:
- I can not build the generator at this frequency using 74HCU04, as it is not up to speed. I can use something like 74F04, with this chip producing TTL output rather than CMOS. It may be an issue because VDP's specification for XTAL input for high level is minimum 3.5 V. The pro of this implemenetation that I may have trimming cap to adjust frequency for normal operating conditions.
- I can build generator using 42,95454 MHz full size clock generator. I have found one source to purchase these generators, and it seems frequency is not that popular - did not find such on Digikey or Mouser. The con of this solution is that its frequency is not adjustable, spec for the device says 50 ppm, which gives 42,95454 * 0.00005 = 2147 Hz spread, and spread for VDP clock (/2) will be 1074 Hz and for encoder (/3) will be 716 Hz. This sounds too much out of the NTSC spec - most video tuning manuals state that spread must be maximum 20 Hz deviation from the 3.579545 MHz, thus for 4*Fsc must be within 80 Hz.
From your experience, what route must I go? Try to find 5 ppm full size clock generator (do such exist at all)? Use faster CMOS chip with circuit having trimming cap to adjust freq? Or maybe I still can keep original 21.47727 MHz clock and divide it to 1.5 somehow other ways I cited above?