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I am reverse-engineering a board which has a Xilinx Spartan 3E FPGA, with VCCAUX powered by a 2.5 volt regulator. Below is the PCB layout for the regulator part of the circuit, and something seems very fishy to me.

enter image description here

My apologies for the horrible pixelation, this was the highest resolution I could get with the equipment I had available. Anyway, the SOT23-5 component labeled "LFSB" is a Texas Instruments LP3988IMF-2.5 linear voltage regulator. I have traced out the schematic below from the board layout:

enter image description here

You may already have noticed the source of my confusion: I have no idea why they would have placed a 316 ohm resistor directly across the output of a 2.5 volt regulator. All that does is waste 7.9 milliamps. I cannot seem to find any reason for doing this. I wonder if it is a design flaw, and that resistor is actually supposed to be connected to the PG pin instead of to ground. I have triple-checked the original PCB, though, and it definitely connects to ground and the PG pin is not connected to anything. If this is an error, however, it would explain why they used a separate trace on the low side of the resistor instead of connecting it to the copper ground pour that's right there. I also wondered if the regulator may require a minimum load in order to maintain a stable output, but that is not the case for this regulator. There are no minimum load requirements. I also considered the possibility that it was intended to bring up VCCAUX more slowly for sequencing purposes for the FPGA, but reading the datasheet this also does not seem to fit - there are no strict sequencing rules for powering up the Spartan 3E.

Can anyone think of a reason why someone would intentionally place a 316 ohm resistor directly across the output of a 2.5V regulator? I considered it might be a bleeder resistor for the output capacitor, but it seems like too low of a value for that.

EDIT: Perhaps this additional information will help. The datasheet for the Spartan 3E specifies what the VCCAUX supply is used for:

VCCAUX: Auxiliary supply voltage. Supplies Digital Clock Managers (DCMs), differential drivers, dedicated configuration pins, JTAG interface. Input to Power-On Reset (POR) circuit.

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  • \$\begingroup\$ Are you certain the one end of that resistor is grounded? That regulator doesn't even require any minimum load to remain stable. \$\endgroup\$ – brhans Jun 29 at 14:05
  • \$\begingroup\$ I am absolutely positive that the lower side of the resistor is grounded. I forgot to mention that I had also considered minimum load requirements, but as you have noted that is not applicable for this regulator. \$\endgroup\$ – DerStrom8 Jun 29 at 14:11
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    \$\begingroup\$ I suspect it has to do with the regulator not providing any reverse current protection. It is chosen empirically so that all capacitors connected to the output discharge more quickly than the input voltage is expected to drop during a power down. \$\endgroup\$ – The Photon Jun 29 at 14:53
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    \$\begingroup\$ @TimWescott No, the 2.5V ONLY goes to the VCCAUX pins of the FPGA, and VCCAUX is not used to power I/O. \$\endgroup\$ – DerStrom8 Jun 29 at 18:02
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    \$\begingroup\$ @Justme Yes, I measured it. The code on the resistor is 49A. The EIA-96 standard is used for coding of 1% SMD resistors, which consists of numerical codes 1-96 followed by a letter, A/B/C/D/E/F/H/R/S/X/Y/Z. The numerical code indicates the value and the letter indicates the multiplier. In this case "49" corresponds to "316" and "A" corresponds to a multiplier of "1". Therefore, the value is 316 * 1 = 316 ohms. \$\endgroup\$ – DerStrom8 Jun 29 at 18:07
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I would have done the same design, in order to reduce dynamic and static load regulation error.

The details for the reasons are evident in the datasheet.

  • look at dynamic load regulation error and input step regulation error.

  • I can only guess what error budget the designer had in mind, but it common for every LDO to have the above responses , although this FET LDO is exceptional low power and dropout voltage.

    • 5mV error {input step=0.6V} with 1mA step load, 200mV error with 150mA step load*
    • the static load regulation error is only rated above 1mA as 0.007%/mA . This implies it is worse below 1 mA and improves with a dummy load of 7.6mA to the designers satisfaction. It also improves dynamic step load regulation error above.*

This 1mA ensures the rise fall time of Gate drive to speed up response. 7.6mA is even better with diminishing returns above this.

  • static load regulation error is only due to RdsOn of the PFET used in the LDO divided by its internal Loop gain. This true for any voltage regulator whether it is FET or BJT. But infinite loop gain can increase stability errors or more ringing, under certain load , (ESR, C ) conditions so it is finite.

Fishy? No way

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    \$\begingroup\$ You too will get more experience. I have 40 yrs of this. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 29 at 18:30
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    \$\begingroup\$ Or think of the step load as a step current sink and the LDO as a voltage source with some GBW limit. this ALWAYS limits slew rate in any linear drive and even Logic IC’s driving load pF. This lag or slew rate in error feedback produces the error +/- glitch on output voltage stepping up + or down - load current. this is a standard stability test for any voltage regulator. OFTEN DONE by 10% to 100% to 10% to give better results than 0 to 100%. So preload if your actual load is 0 static and high dynamic. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 29 at 19:12
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    \$\begingroup\$ it depended on the application current crest factors and steady state load (uA) . no magic number in datasheet, but I would have considered 5% max rated current as a preload as a starting point then confirm all sources of regulation error (static, step source V and step load I) to derive one with the best margin for variations in part GBW. This is a mandatory concern for mobiles with low Rx power and high Tx power yet minimize wasted power in order to,achieve the RF stability during carrier burst ON. it seems the designer has the same wisdom, as 5% of 150mA is what? \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jun 29 at 20:19
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    \$\begingroup\$ @SunnyskyguyEE75 "5mV error with 1mA step load, 200mV error with 150mA step load" - I can see the 150mA step load response in figure 15/16 of the datasheet, but where are you finding the 1mA step load response of 5mV error? I've combed through the datasheet, but I can't seem to find it... \$\endgroup\$ – marcelm Jun 30 at 13:32
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    \$\begingroup\$ Good Eye @marcelm It was actually 9.2.3 line in step +/-0.6V then "5mV error with 1mA load, \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 1 at 12:49
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As already suggested by some other comments that 316 ohm resistor is placed there to allow the voltage regulator circuit some ability to sink some current in the case that the 2.5V rail gets some leakage from a higher voltage rail. That leakage would typically cause the regulator output to shut off and to rise up and go to a higher voltage. A designer makes a design tradeoff between how much sink capability to allow for versus the amount of extra load the resistor places on the voltage regulator.

Leakage conditions can exist during power on and power off sequencing of complex semiconductor devices and the sink capability can be important to keep things in check.

In some cases the voltage regulator may have a feature called over voltage lock out that shuts down the regulator if the output rises up too much. This can be detrimental to system operation, especially if the power good (PG) indicator pin is monitored to control a voltage regulator chain on a complex board. The current sink resistor can play a role of preventing an unexpected shutdown due to a small amount of leakage into a particular rail.

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I am not convinced that the resistor is grounded. I have labeled the parts and the copper pours as per your "reversed engineered" circuit.

enter image description here

If R14 was grounded, why would a via be wasted when there is GND pour right next door to it. How did you test it was ground? did you just buzz between lines? There is a very high chance there is an LED to ground hanging off that via. This would provide a visual indication 2.5V is powered and a resistor around 316R would be ok for a RED/YELLOW/GREEN LED ( 4mA). This would aos give the "indication" of a short if you mis-read a DMM or depending on specifics of the DMM.

https://reference.digilentinc.com/_media/s3e:spartan-3e_sch.pdf This is a reference design for a Spartan 3E. There is a 2k2 loading on the 2.5V regulator but also an LED off the 3v3. This could be to provide some damping to the circuit downstream

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    \$\begingroup\$ If R14 was grounded, why would a via be wasted when there is GND pour right next door to it. I mentioned this in my original post as well. It didn't make any sense to me either. How did you test it was ground? did you just buzz between lines? I measured between multiple known ground points, in resistance mode, continuity mode, and diode mode. Continuity and resistance mode show 0.2 ohms and diode mode shows 0 volts, indicating a clear short. There is a very high chance there is an LED to ground hanging off that via. There are no LEDs on this board. 2.5V only connects to FPGA VCCAUX \$\endgroup\$ – DerStrom8 Jun 29 at 15:26
  • \$\begingroup\$ Could the via be connecting to a different ground? Perhaps it's going to AGND when the pour next to it is DGND, or something like that? \$\endgroup\$ – Hearth Jun 29 at 16:30
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    \$\begingroup\$ @Hearth that would be an incredibly bad decision (but possible...). Split grounds are a thing of the past BUT more importantly, the current wants to return to its source, which is near pin2 of U4. Always think about the return path \$\endgroup\$ – JonRB Jun 29 at 17:18
  • \$\begingroup\$ @JonRB I don't know much about high-speed digital design, so I'm just throwing out a guess. It didn't seem like a sensible choice to me, but then neither does adding that via. \$\endgroup\$ – Hearth Jun 29 at 17:40
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    \$\begingroup\$ Is that a multi layer PCB or what’s on the backside of that via? \$\endgroup\$ – eckes Jun 30 at 11:03

protected by Dave Tweed Jun 30 at 11:18

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