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I am very new to Verilog, and I found the need to use "generate loops" to instantiate multiple hardware blocks. In this case, I am instantiating multiple "pe" blocks, a block which performs some simple arithmetic.

Code is shown below:

// intermediate signals
reg init_temp;
reg [D_W-1:0] in_a_temp;
reg [D_W-1:0] in_b_temp;
reg valid_D_in_temp;

genvar i, j;
generate
        for (i=0; i<N; i=i+1) begin : pe_generate_i
                for (j=0; j<N; j=j+1) begin : pe_generate_j
                        if ((i == 0) & (j == 0)) begin
                                valid_D_in_temp <= (pixel_cntr_A == M-1);
                                init_temp <= (pixel_cntr_A == M-1);
                                in_a_temp <= A[0];
                                in_b_temp <= B[0];
                        end else if (j == 0) begin
                                in_a_temp <= A[i];
                                valid_D_in_temp <= valid_D[i-1][j];
                        end else if (i == 0) begin
                                in_b_temp <= B[j];
                        end else begin
                                valid_D_in_temp <= valid_D[i][j-1];
                                init_temp <= gg;
                        end

                        pe pe_inst (
                            .clk(clk),
                            .rst(rst),
                            .init(init_temp),
                            .in_a(in_a_temp),
                            .in_b(in_b_temp),
                            .valid_D_in(valid_D_in_temp),
                            .out_sum(),
                            .out_b(),
                            .out_a(),
                            .valid_D(),
                            .init_out()
                        );
                end
        end
endgenerate

A syntax error arises in the first non-blocking statement: valid_D_in_temp <= (pixel_cntr_A == M-1);

Error:

# ** Error: (vlog-13069) systolic.sv(37): near "<=": syntax error, unexpected <=.
# ** Error: systolic.sv(37): (vlog-13205) Syntax error found in the scope following 'valid_D_in_temp'. Is there a missing '::'?

Can anybody suggest what the problem might be?

Thanks in Advance

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Basically, you can only use <= inside an initial or always process block.

If you want to have logic inside your generate block in addition to module instantiations, you need to wrap it in an always @* ... or use assign ... statements.

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You have multiple errors.

You should see a generate for loop as a "please instance the following code multiple times" followed by the code to instance.

Thus an assignment should be that:

assign valid_D_in_temp <= (pixel_cntr_A == M-1);
assign init_temp <= (pixel_cntr_A == M-1);
// etc.

But that code is wrong too as it uses non blocking assigns <= while an assign should use blocking =. Also you can't use if very well with that.

So at the moment your code is a mixture of code that should probably be in an 'always' statement and assignments which should be outside an 'always' statement. I don't know what you are trying to do so I can't tell you how the code really should look like.

I hope you are aware that the pe pe_inst ( block will be instantiated (repeated) N*N times....

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  • \$\begingroup\$ Thanks for the suggestion. I definitely want to instantiate pe N*N times. All that logic above the "pe pe_inst (" line of code is to specify which signals will be driving the inputs to the pe_instances. Thus, I will definitely change non-blocking assignments to assign statements (don't know why I initially put non-blocking statements) \$\endgroup\$ – Universal Thinker Jun 30 at 13:59

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