# JFET stabilised wien bridge component ratios

I find myself in need of a sine wave oscillator and have decided on the wien bridge. I have followed all the tutorials but have a few questions that do not seem to be answered elsewhere. Firstly, I understand the ratio between Rf and R3 determines the negative feedback loop gain set to 3, or just above, at a ratio of 2:1. But there are lots of combinations of resistances which would give that ratio, so what effect would say using a 1 OHM : 2 OHM resistance be compared to 10 OHM : 20 OHM? And the same question about the capacitor resistor combinations in the lead lag circuit.

Second, how do the values of Rf and R3 get selected when there is a JFET paired with R2? I figured that to get a gain of 3 after the gate voltage comes up then I would add the Rds(on) of the JFET to R3 and count them as one, so then when the JFET is off, there would be no resistance through it and the gain would be higher than 3, allowing oscillations to start. Is this correct? Any particular ratio between the JFET Rds(on) and R3, does one dominate, equal or does not matter?

Third, the negative peak detector which drives the gate of the JFET charges a capacitor, which has a resistor in parallel. What is that resistor R4 doing and how is its value determined? How is the capacitors value determined?

Lastly, what determines the output voltage? Say, I need a 0.1 v output to feed a BJT amp, what values would I need to change and how would I calculate them? I figured the output would be determined by the maximum peak to peak printed on the datasheet, but how would I bring this down?

Thanks for any replies

Regarding the control loop Diode-C3-R4:

This is not a peak detector because the parallele resistor R4 continuously discharges the capacitor which - in turn - is charged by the output amplitude (if it can open the diode at a certain level). This is necessary in order to allow amplitude control in BOTH directions. The opamp gain swings around the nominal value of "3".

Hence, the output amplitude is NOT CONSTANT - it will exhibit a small amplitude modulation which is determined by the time constant C3-R4. This time constant should be at least ten times larger than the oscillation period. From this requirement you can select both values (C3 and R4).

Regarding the ouput amplitude: An exact computation is not possible (due to the nonlinear Diode characteristics). However, a good estimat is possible if you know the nominal value (during steady-state oscillations) of the FET resistance and the corresponding gate voltage. This give you the mean voltage across C3 and - together with app. 0.5 across the diode - a reasonable guess for the corresponding output amplitude.

EDIT (error correction): There is a logical error on your side.

You wrote: .....when the JFET is off, there would be no resistance through it and the gain would be higher than 3, allowing oscillations to start.....

No, when the JFET is off the RDS resistance is very large and the opamp works as a unity gain amplifier (full feedback).

The correct description is as follows: At t=0 the ouput voltage (and the gate voltage) is zero and the FET is open - the RDS resistance is low (max current ID) and the gain larger than "3". Now - for rising amplitudes the gate voltage becomes more and more negative and the RDS resistance goes higher and provides more negative feedback (the gain is decreased until it reaches "3").

• would the time constant be 5RC or just RC? – benDR Jul 1 at 12:39
• "This is not a peak detector" is incorrect. the +DC biased negative swing is detected as a negative peak detects with diode to attenuate negative feedback and boost gain so it starts up FASTER, diode R= << 100 Ohms say, and R4 is probably 10k to 100k to so fast start RC the slow decay on peak detector to reduce distortion settling on unity gain. – Tony Stewart Sunnyskyguy EE75 Jul 1 at 13:18
• Although I spent little time making perfect grammar organizing each question with an answer, at least I answered every question and had no major technical error. but had minor confusing sentence ( agreed :} – Tony Stewart Sunnyskyguy EE75 Jul 1 at 13:45
• -1 THis is not a peak detector. (Wrong) – Tony Stewart Sunnyskyguy EE75 Jul 1 at 19:53
• Technically this diode RC acts as a "Quasi-peak detector" where the ideal signal BW ought to be a small % of oscillator frequency for low phase noise and low THD. consequently, this design has too high a feedback gain and BW and is very distorted. Unlike my optimized design. you are thinking of a DMM Vpk and hold detector, which it is not. It is just a quasi peak detector that should hold a bit longer than it does. So there is no effective "quasi" filter and it becomes thus becomes *a negative peak detector like in a spectrum analyzer with no video filter uses a peak detector + or - – Tony Stewart Sunnyskyguy EE75 Jul 28 at 16:37

Rf is a load on the opamp output. Its value cannot be less than 2k ohms for most opamps so maybe use 20k ohms. Then the resistance of the Jfet plus R3 must be 10k ohms for a gain of 3. Let R3 be maybe 4.7K then the Jfet can be 5.3k.

R4 discharges the capacitor and allows the Jfet to turn on when the output signal level is low. The capacitor value is selected to be a good filter at the lowest frequency you want low distortion.

Allow the output level to be high enough for the circuit to work well, then attenuate it with two series resistors to ground at the output.

• I rather think, the task of the capacitor C3 is not to "filter" anything but to provide a - more or less - fixed DC voltage at the gate of the FET. As I have explained in my detailed answer, the time constant C3R4 causes a small amplitude modualtion of the output signal (which is quite normal because steady-state oscillations exactly at unity loop gain can never be achieved). – LvW Jul 1 at 9:17
• thought most jfet Rds(on) values were around 150 - 400 ohms? 4.7k seems high – benDR Jul 1 at 10:28

## Update July 28

The output level is determined by the Vgs threshold required to make the loop gain exactly unity for a pure sine. Since there is a Thevenin R5/(R5+R7) ratio with a diode offset which is nulled by another voltage reference (0.75V) in my answer so become a better negative peak detector with an initial condition to get an instant startup of an infinite Q ( or really highQ at steady state ( See filter response in linked answer)) oscillator, and also the FET Vt determines the output amplitude so this 0.75V precharges the cap voltage to Vgs to start with a sine wave.

THus to reduce Vout sine, use a lower Vt and higher ratio of R7/R4. Conversely for a maximal Vout, use a higher Vt and and lower R7/R4 =1 as in my case.

I could have simplified the design to incorporate this bias, but chose not to.

"This is not a peak detector" is incorrect. the +DC biased negative swing is detected as a negative peak detects with diode to attenuate negative feedback and boost gain so it starts up FASTER, diode R= << 100 Ohms say, and R4 is probably 10k to 100k to so fast start RC the slow decay on peak detector to reduce distortion settling on unity gain. ( JFET has Id=Idss with Vgs=0V which then conducts but also introduces DC offset so output saturates, (not so great) :(

• peak detectors have some slow decay rate controlled here by R4C3gm where gm=ΔId/ΔVgs ~ 20m to 50m for some

• the closed loop positive feedback must be slowly regulated to “1.000” depending compression rate of change of FET attenuator vs frequency to satisfy oscillation criteria

• you will see the DIODE attacks fast to bias the JFET ON to reduce the

• for an interactive simulation with a tuning pot read my better answer

• always start with THD specs or amount of asymmetry of the sinewave, with output Vpp levels defined and startup time inverse with Q that defines this high Q resonator.

• there are better designs but depends on all your specs for linearity, amplitude, phase noise and startup time, frequency, and controllability, ranges and tolerances, and tuning methods.

did you search here for WIEN BRIDGE or Wein (x)

## Design Requirement:

Rf:R2 = 2:1 in the steady state but when 1:1 will startup faster as an oscillator. Thus negative peak detector decay rate dV/dt on output on R4 times gain gm must be defined for low gain at frequency of oscillation so result is a symmetrical sine with low distortion

Rf, R4 absolute values that are too low like 1,10,100 Ohms are bad for Op Amps to drive this ( too high a current) and Jfet resistance cannot get this low and 1M is almost too high so what happens if you choose values in between and

how does gm change with Vgs? i.e. where is it maximum? Answer: Idss mA is defined by Vgs=0V which produces maximum gm but is reduced only slowly as Vgs rises, then sharply reduces. Sensitivity only needs to <<1% gain control and this is far too great without attenuators.

This allows a wide tolerance but almost full swing sine output limited also by the "headroom" needed for Op Amp (Vout max+ Vout min) for BJT types vs CMOS Op AMps that are Rail to Rail.

• startup time vs THD harmonic distortion ( inferior design to Commercial sig generator but cheap and dirty)

Lastly won't need 0.1V to a BJT amp as this is alarge voltage swing oscillator. But you need more current drive, then include two transistors as "emitter followers" PNP+NPN to OpAmpout before feedback. (common easy search will show how)

After careful tuning for low distortion and instant startup , amplitude gain control sensitivity reduction and with resistors with Vbias 0.75V+/-20% to put JFET into proper pre-condition for rapid locking to peak detector ,this is what an excellent sine Oscillator should look like. My optimization were done before but shown now.

• Comments are not for extended discussion; this conversation has been moved to chat. – clabacchio Jul 5 at 14:35
• @clabacchio have you ever seen a better performing Sine WIEN Osc. – Tony Stewart Sunnyskyguy EE75 Jul 5 at 17:28
• A peak detector detects - and holds - the peak value of a periodic signal. However, in our case and under stwady-state conditions, the diode-C-R combination causes the voltage across the capacitior to swing (just a little bit and slowly) around a voltage which is well below the peak value at the opamps output. This is a desired feature and is caused by the continiuous charging/discharging of the capacitor. Each simulation shows this effect. – LvW Jul 28 at 11:26
• A peak detector simply rectifies voltage with a storage capacitance and series and parallel R's affect the rise and decay time. . In this case it is a negative peak detector with a Thevenin voltage and resistance due to R5//R7 * 300pF rise time and R7*300pF decay time. In my design this is 10M/10M * 1nF rise time and 10M * 1nF decay time thus giving much lower BW in the rate of change of FET transconductance as this gain does not require such a large swing at the stable operating point. It is still a negative peak detector for AGC and my design is far superior due to this @LvW ok? – Tony Stewart Sunnyskyguy EE75 Jul 28 at 12:54
• @clabacchio do you understand or agree? LvW you are thinking of a peak and hold detector that holds for a much larger ratio of decay/rise time to store an accurate peak longer than it decays. So there is a linear aspect to all peak detectors due to these two time constants. YOur thinking is that is only for large ratios. Tf>>Tr yet Tr is never 0 and Tf is never infinite. They are analog and it is still a peak detector. although lossy due to Thevenin ratios. R5/(R5+R7) – Tony Stewart Sunnyskyguy EE75 Jul 28 at 12:56