Update July 28
The output level is determined by the Vgs threshold required to make the loop gain exactly unity for a pure sine. Since there is a Thevenin R5/(R5+R7) ratio with a diode offset which is nulled by another voltage reference (0.75V) in my answer so become a better negative peak detector with an initial condition to get an instant startup of an infinite Q ( or really highQ at steady state ( See filter response in linked answer)) oscillator, and also the FET Vt determines the output amplitude so this 0.75V precharges the cap voltage to Vgs to start with a sine wave.
THus to reduce Vout sine, use a lower Vt and higher ratio of R7/R4. Conversely for a maximal Vout, use a higher Vt and and lower R7/R4 =1 as in my case.
I could have simplified the design to incorporate this bias, but chose not to.
"This is not a peak detector" is incorrect. the +DC biased negative swing is detected as a negative peak detects with diode to attenuate negative feedback and boost gain so it starts up FASTER, diode R= << 100 Ohms say, and R4 is probably 10k to 100k to so fast start RC the slow decay on peak detector to reduce distortion settling on unity gain. ( JFET has Id=Idss with Vgs=0V which then conducts but also introduces DC offset so output saturates, (not so great) :(
peak detectors have some slow decay rate controlled here by R4C3gm where gm=ΔId/ΔVgs ~ 20m to 50m for some
the closed loop positive feedback must be slowly regulated to “1.000” depending compression rate of change of FET attenuator vs frequency to satisfy oscillation criteria
you will see the DIODE attacks fast to bias the JFET ON to reduce the
for an interactive simulation with a tuning pot read my better answer
always start with THD specs or amount of asymmetry of the sinewave, with output Vpp levels defined and startup time inverse with Q that defines this high Q resonator.
there are better designs but depends on all your specs for linearity, amplitude, phase noise and startup time, frequency, and controllability, ranges and tolerances, and tuning methods.
did you search here for WIEN BRIDGE or Wein (x)
Design Requirement:
Rf:R2 = 2:1 in the steady state but when 1:1 will startup faster as an oscillator. Thus negative peak detector decay rate dV/dt on output on R4 times gain gm must be defined for low gain at frequency of oscillation so result is a symmetrical sine with low distortion
Rf, R4 absolute values that are too low like 1,10,100 Ohms are bad for Op Amps to drive this ( too high a current) and Jfet resistance cannot get this low and 1M is almost too high so what happens if you choose values in between and
how does gm change with Vgs? i.e. where is it maximum?
Answer: Idss mA is defined by Vgs=0V which produces maximum gm but is reduced only slowly as Vgs rises, then sharply reduces. Sensitivity only needs to <<1% gain control and this is far too great without attenuators.
This allows a wide tolerance but almost full swing sine output limited also by the "headroom" needed for Op Amp (Vout max+ Vout min) for BJT types vs CMOS Op AMps that are Rail to Rail.
- startup time vs THD harmonic distortion ( inferior design to Commercial sig generator but cheap and dirty)
Lastly won't need 0.1V to a BJT amp as this is alarge voltage swing oscillator. But you need more current drive, then include two transistors as "emitter followers" PNP+NPN to OpAmpout before feedback. (common easy search will show how)
After careful tuning for low distortion and instant startup , amplitude gain control sensitivity reduction and with resistors with Vbias 0.75V+/-20% to put JFET into proper pre-condition for rapid locking to peak detector ,this is what an excellent sine Oscillator should look like.
My optimization were done before but shown now.
