I'm just looking for some extra resources for thermal impedances of JEDEC standardized packages. I've already found one such article posted by JRC, https://www.njr.com/semicon/package/thermal.html , and another by LT, https://www.analog.com/media/en/package-pcb-resources/package/thermal-table.pdf. I was just wondering if there was another resource for typical thermal impedance values for commonly used packages that anyone on here uses. I also attempted to search on the JEDEC website to see if the parameters for packages included typical thermal impedances but for some reason I couldn't even find the JESD30G document that is supposed to contain all of package information. Any help would be appreciated. I'm planning on using this for ICs where the thermal impedance is not listed in the datasheet or online, but it does contain package information so for now I am just trying to compile information.
The black plastic has Rthermal about 100X that of copper or silicon.
In many packages the plastic distance, between silicon die and the various metal leads, sets the total thermal resistance.
The manufacturer can pick various CAVITY sizes; large cavities and small die will have long bond wires (more gold cost, and more thermal resistance at 10,000 degree Cent per watt), and will require lots of plastic between sides of the silicon die and the pins.
For lowest thermal resistance, you must XRAY the product and ensure the die almost totally fills the cavity.
So if you really care about 150 degree C per watt, versus 200 degree C per watt, you need to write a specification directed to the IC packaging engineer (inhouse, or a contract house) and probably have an INSPECTOR on the assembly line, to ensure your ICs use the package with the cavity that fits snugly (a few mils larger) around the die.