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I have some VHDL code written for synthesis with three instances in the top level and the three subs so I can pass inputs and outputs. Call them top, sub1, sub2, sub3. I now want to add a signal and use it as a flag across the top and all subs. For example.

signal  flag: std_logic_vector(3 downto 0):= "0000";

On each sub and the top page, I want to read/write to this signal so I can trouble shoot and start one subroutine after one sub is complete or other variations using the flag values. I can assign "flag" as a port and give it direction but it seems cumbersome. I then saw "hierarchical names" and I tried the following inside of top in my list of signals.

alias flag is
<< signal sub1 : std_logic_vector(3 downto 0)>>;

In sub1, sub2, sub3, I would have the following, from my understanding:

   signal  flag: std_logic_vector(3 downto 0);

I then get a syntax error near "<" and ">". How do I get this to work? I am using VHDL-2008.

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  • \$\begingroup\$ IEEE Std 1076-2008 6.6.2 Object aliases "The following rules apply to object aliases: ... b) If the name is an external name, a subtype indication shall not appear in the alias declaration. ..." What's a 'sub' here? It's not VHDL nomenclature. Provide the entire error message which will also identify the tool. Synthesis tools generally don't support external names, which might explain the syntax errors. Signals declared in packages are generally not supported either, that'd leave ports interconnecting the hierarchy. \$\endgroup\$ – user8352 Jul 1 '19 at 23:55
  • \$\begingroup\$ sub1 is the name of the file being instantiated. Here are the errors: Error (10500): VHDL syntax error at test_top.vhd(187) near text "<"; expecting an identifier, or a string literal Error (10500): VHDL syntax error at test_top.vhd(187) near text ">"; expecting ";", or ":=", or "bus", or "register" \$\endgroup\$ – Tyler314 Jul 2 '19 at 0:32
  • \$\begingroup\$ Quartus, which doesn't support external signal names in synthesis. You could add the error message to your question. \$\endgroup\$ – user8352 Jul 2 '19 at 1:08
  • \$\begingroup\$ I have 4 different files in my project. The top file and three different files each represented by a different task. Each file has to communicate back to the top file as well as receive start instructions from the top file and others. Currently, it takes 4 INs and 4 OUTs configured as ports, making it very cumbersome. It sort of defeats the purpose of separating tasks. Is there another way to communicate between the tasks that is not so confusing? \$\endgroup\$ – Tyler314 Jul 2 '19 at 1:39
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    \$\begingroup\$ What's not shown in your question can't be seen as confusing by your readers. Seems no more confusing that an arbiter. \$\endgroup\$ – user8352 Jul 2 '19 at 2:02
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This syntax might be helpful to you. Put a colon next to "is".

alias flag is: << signal sub1 : std_logic_vector(3 downto 0)>>;

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