I have some VHDL code written for synthesis with three instances in the top level and the three subs so I can pass inputs and outputs. Call them top, sub1, sub2, sub3. I now want to add a signal and use it as a flag across the top and all subs. For example.
signal flag: std_logic_vector(3 downto 0):= "0000";
On each sub and the top page, I want to read/write to this signal so I can trouble shoot and start one subroutine after one sub is complete or other variations using the flag values. I can assign "flag" as a port and give it direction but it seems cumbersome. I then saw "hierarchical names" and I tried the following inside of top in my list of signals.
alias flag is << signal sub1 : std_logic_vector(3 downto 0)>>;
In sub1, sub2, sub3, I would have the following, from my understanding:
signal flag: std_logic_vector(3 downto 0);
I then get a syntax error near "<" and ">". How do I get this to work? I am using VHDL-2008.