Filtering an ADC input with an RC low-pass filter

I use an instrumentation amplifier to amplify low voltage signals from a sensor. The max. amplified output voltage is 3V. Im using this ADC: http://ww1.microchip.com/downloads/en/DeviceDoc/22088c.pdf. It has 4 channels that are multiplexed. Every 5 seconds all 4 channels should be sampled with 18bit mode (3.75 SPS). The internal sampling capacitor of the ADC is 3.2pF. I have put a RC low-pass filter like you can see in the following schematic in front of every ADC input channel. I realized that there is a significant voltage drop accross the 100kOhm resistor expecially (about 60mV drop for a 1.5V amplifier output voltage). Now my question is, why is that? What values from the datasheet of the amplifier do i need and how can i calculate what is happening here? Do I need to take the leakage current to compute an average current? As this is a delta sigma ADC, im not sure what frequency I need to take to make calculations. I hope you can point me into the right direction. I also want to use C2 as a resevoir for the sampling capacitor because im multiplexing between multiple channels and I do not want to offset the current measurement with some voltage of a previously sampled channel. Hints, specifications and formulas I need for this to calculate would really help a lot! Thank you very much.

simulate this circuit – Schematic created using CircuitLab

• 60 mV over 100 kΩ is only 0.6 µA. Why the two filters in a row? Having 100 kΩ between C2 and the ADC input would defeat its purpose as a reservoir cap. Jul 3, 2019 at 0:29
• What do you want your cutoff frequency to be? Jul 3, 2019 at 0:30
• Most ADC inputs need a source impedance less than 1 kohm. A 100k resistor would cause severe errors in the reading.
– user105652
Jul 3, 2019 at 1:12
• This type of ADC needs a low source impedance. From the datasheet: The conversion accuracy can be affected by the input signal source impedance when any external circuit is connected to the input pins. The source impedance adds to the internal impedance and directly affects the time required to charge the internal sampling capacitor. Therefore, a large input source impedance connected to the input pins can degrade the system performance, such as offset, gain, and Integral Non-Linearity (INL) errors. Ideally, the input source impedance should be zero. Jul 3, 2019 at 1:19
• Yes, sorry! I made a stupid mistake in the schematic, I fixed it now. I wanted to cascade two poles to have sharper filter characteristics. I would like start filtering at low frequency already to filter out 50/60Hz for sure but even below that. (cutoff at about 10Hz maybe) Thank you very much for the comments! Jul 3, 2019 at 1:20

Why does the ADC draw an input current?

Assume that ADC grabs a voltage sample of the input signal, with that voltage stored on a 10pF capacitor; with these 18 bit ADCs using the over-sampling method, assume 1,000 samples are used to provide a fine 18-bit value. And assume Vin = 3volts.

What do we know

Iinput = F * C * V = 1,000 samples/conversion * 10pF * 3v = 1e+3 * 1e-11 * 3

Iinput = 1e-8 * 3 = 0.1uA * 3 = 0.3uA input current for ONE CONVERSION PER SECOND.

• thank you for your answer. How do you come up with the 1000 samples for F? wouldnt I need to oversample much more if I go for 18bit? As oversampling 2^2N times yields N bit increase? Jul 3, 2019 at 17:54
• @ Henry older oversampling ADCs need 2^N samples, but can use extremely sloppy internal DACs in the combined analog-digital tracking loop. If you have better (onchip) DACs (or possibly self-calibrating DACs, or DACs usng pseudo-random combining of a number of poorly-matched DAC elements that average to produce a statistically-predictable excellent DAC), then 2^N is not longer required. You should read online about "high-order oversampling loops", some using multiple feedback paths. Jul 4, 2019 at 4:54
• nice info thanks! How do you come up with 1,000 samples/conversion in your post to calculate the average current? Can you please tell me what values you took from the datasheet of this ADC: ww1.microchip.com/downloads/en/DeviceDoc/22088c.pdf Because calculating the current like you told me in this post does not match with my measurements, my voltage drop across my RC pole is much higher unfortunately... Jul 4, 2019 at 4:58
• @ Henry Having no details on the 18-bit ADC "modulator", I provided you an example computation, to explain your "why is that voltage drop". If you want a lower voltage drop, given you cannot control the Fsample nor the Csample nor the Vin, your only choice is to reduce the resistors. Jul 4, 2019 at 13:01
• ok, thanks. Here you proposed a filter for the same ADC with an even much higher value resistor: electronics.stackexchange.com/questions/418009/… . I did not know that you just made an example, due to the provided simulation I assumed that you took data from the ADCs datasheet to construct the filter that you proposed. Jul 4, 2019 at 14:41

The source Resistance is too high for the input impedance or DC current drain. 1.5V/60mV * 0.1MOhm = Rin (Equiv)=2.5MOhm

Y answer to unstated question & problem

The real requirement should be a DC error lower than your ADC resolution.

also ...

The sample bandstop attenuation needs to be checked.

Your low sampling rate Nyquist frequency Fs/2 i.e. the attenuation in -dB at this breakpoint should reduce your input spectrum below your ADC resolution.

• this depends on your unstated spectrum could be up to -20log2^x for x bit resolution but depends on type of ADC and spectral response desired. E.g. -60 dB at 1Hz. Or else oversample at a higher rate and decimate.

TL;DR FYI only https://www.osti.gov/servlets/purl/1137235

• Fig 2.11 shows -20 dB / decade response yet sharp response between Nyquist and sampling rates so Fourier spectrum of 0.35/T rise time = f-3dB then -40dB / decade with 2nd order another -40dB/decade or 24dB/octave below f-3dB (or odd harmonics only, assuming triangle wave for Temp. Ramp up/down)
• thus dt*Fs= 18s*3.75Hz= 67 = 2^6 = 6 octaves or -144 dB from full scale with a dynamic range without filtering with a 18 bit dynamic range or 108 dB
• so you need only 36 dB of attenuation filtering at > 4Hz of or -12db/octave a breakpoint of 2nd order at 3 octaves down or <0.5 Hz for your 2nd order LPF with a Gaussian Response to minimize group delay.

This assumes you are aware of Fourier response for a triangle wave, and 2nd order LPF with conversion of log2 to log 10 , and no proof needed for simple constants used in my evaluation like -6dB/oct. per LPF order and -12db/oct. for a ramp signal and Tr to -3dB BW conversion.

Conclusion

• you will have some aliasing errors on your fastest slew rate due to your low pass filter being too high greater than your resolution, but since you have no accuracy spec, I only used resolution for this highest slew rate of 16 seconds full scale.
• Thank you, but now i updated my schematic as you see. But still the current voltage drop is too big, dont u think? I would expect it to be somewhere around the micro range. How does the leakage current of the ADC effect this drop? do i need to include it into the voltage drop calculations somehow? Jul 3, 2019 at 18:06
• @Henry You need a better design as the Series R To R load ratio causes your DC drop. Like an Op Amp with a 6th order LPF below Fs/2 for sampling rate=Fs. capiche? Didn’t you read my link? Jul 3, 2019 at 19:31
• I did, didnt answer my question tho interesting info, thanks. i can not use additional active components on my board. need to stay passive. As i asked in my comment im more concerned where this voltage drop is commin from. it shouldnt be so big. how would you calculate it? can you confirm with ur calculations that there can be such a big voltage drop? What would be the oversampling frequency for my delta sigma with 18 bit mode? Jul 3, 2019 at 19:51
• Please check page 4 and 5 of this: osti.gov/servlets/purl/1137235 . How do I determine the oversampling frequency of a delta sigma ADC? Jul 3, 2019 at 21:54
• By rejection of defined spectrum or slew rate to desired residual noise level Jul 3, 2019 at 21:55