100 MHz is the clock available in my FPGA board. It feeds Module 2. Module 1 is needs a slow clock of 10 MHz clock. So I used a clock divider with flip flops. I thought of not using PLL to make my code purely RTL. Module 1 is transferring some data along with control signals to Module 2.
My current assumption is that:
The main clock and the divided clock are synchronous, and their phase relations are known to the synthesiser. And hence there is no Clock Domain Crossing here. So that I can simply constraint both the clocks and put multi-path SDC constraints between Module 1 and Module 2.
But I am not sure whether I am right. Is this a case of asynchronous CDC ? Will I need any synchroniser between Module 1 and Module 2 ?
Any feedback is welcome.