Acceptable designing two clock generators using single package?

Question

The circuit I usually use is Pierce oscillator:

(pic source)

I have always had single system clock in the system, built on single HCU04 chip. Now I need two: 6*NTSC and 4*PAL - frequencies not related to each other. It is possible to build both using 6-gate HCU04 chip.

I have 3-rd party design, which has its NTSC clock (3.579545 MHz) passing through the 74LS04 chip, with its other gates used for "less intensive" purposes. I was astonished to see all other gates picking up considerable noise of the NTSC carrier, with ground pin of this chip being also affected by this frequency. Noise was easily seen on the scope, and propagated down the circuits.

I can not find definite discussion or answer for the phenomenon (probably because it is simple and assumed):

• building two clock circuits on single chip will save money and probably space on the board, but gates may suffer from crosstalk through internal power connections within the chip;
• building two clock circuits on a number of chips (e.g. 4 chips 1G each) will minimize crosstalk, I will be able to put decoupling on each chip and optimize their power connection, but it will cost more in terms of components and board space.

Do I understand the situation properly? Is it really beneficial to not use single chip for two generators? What is the best practice in various conditions?

Answer 1

For such extremely unrelated frequencies to be derived from the same clock, your only choices would be

• a fractional-N synthesizer, or
• a digital synthesis with either a very large table or an ad-hoc cosine computation (typically based on a CORDIC).

You can implement the former using standard RF clock synthesizers (LMX2571, MAX2870,…) ; many of them will be specialized for RF generation, so you might need to divide the results down afterwards.

Digitally, I don't know whether there's ready-to-use digital direct synthesis (DDS) chips that have an internal table large enough to allow for sufficient frequency resolution. If you can't find one suitable, a possible way would be implementing a large DDS yourself, e.g. with a medium sized FPGA and enough memory for a sufficiently large table plus a DAC. Alternatively, just calculate \$\cos(2\pi f t)\$ for arbitrary \$f\$ yourself on an FPGA with a couple of multipliers – the CORDIC algorithm family is your friend.