# Acceptable designing two clock generators using single package?

The circuit I usually use is Pierce oscillator:

I have always had single system clock in the system, built on single HCU04 chip. Now I need two: 6*NTSC and 4*PAL - frequencies not related to each other. It is possible to build both using 6-gate HCU04 chip.

I have 3-rd party design, which has its NTSC clock (3.579545 MHz) passing through the 74LS04 chip, with its other gates used for "less intensive" purposes. I was astonished to see all other gates picking up considerable noise of the NTSC carrier, with ground pin of this chip being also affected by this frequency. Noise was easily seen on the scope, and propagated down the circuits.

I can not find definite discussion or answer for the phenomenon (probably because it is simple and assumed):

• building two clock circuits on single chip will save money and probably space on the board, but gates may suffer from crosstalk through internal power connections within the chip;
• building two clock circuits on a number of chips (e.g. 4 chips 1G each) will minimize crosstalk, I will be able to put decoupling on each chip and optimize their power connection, but it will cost more in terms of components and board space.

Do I understand the situation properly? Is it really beneficial to not use single chip for two generators? What is the best practice in various conditions?

• for such extremely unrelated frequencies, your only choice would be a fractional-N synthesizer. – Marcus Müller Jul 3 at 13:04
• Have you confirmed that the noise was in fact passed via the chip and not via the scope? The ground also being affected suggests that perhaps the noise was picked up by the scope, not the circuit. – scorpdaddy Jul 3 at 13:10
• @MarcusMüller I can use two Pierce oscillator circuits? Why making things complicated using two CDCE913 (or single CDCE925). I think I would use CDCE chips (considered it in the first place to generate all the clocks), but I can not source it. – Anonymous Jul 3 at 13:59
• @scorpdaddy I connect ground of the probe to some ground within the circuit, and put probe onto the ground pin of the chip. And see that low amplitude 3.57 MHz signal. Touching other chips' ground pins gives clean ground. Design is made of LS chips, and there's relatively far distance between them. – Anonymous Jul 3 at 14:02
• @Anonymous I was assuming you needed the two clocks to be phase-coherent. – Marcus Müller Jul 3 at 14:37

Digitally, I don't know whether there's ready-to-use digital direct synthesis (DDS) chips that have an internal table large enough to allow for sufficient frequency resolution. If you can't find one suitable, a possible way would be implementing a large DDS yourself, e.g. with a medium sized FPGA and enough memory for a sufficiently large table plus a DAC. Alternatively, just calculate $$\\cos(2\pi f t)\$$ for arbitrary $$\f\$$ yourself on an FPGA with a couple of multipliers – the CORDIC algorithm family is your friend.