PCB layout - ground plane clearance around and under a ceramic resonator

Question

We are using Murata's 4MHz ceramic resonator (CSTCR4M00G53-R0) in one of our designs and request help in PCB layout design around the ceramic resonator. The below Murata's FAQs page suggests not to place any GND plane under the ceramic resonator. Picture in page is attached below.

https://www.murata.com/en-us/support/faqs/products/timingdevice/ceralock/cct/cc0010

We are using a 4 layer PCB with continuous GND plane in layers 1,2 & 4 and continuous power plane in layer 3.

Please help us with the questions below:

1. Should we provide a copper clearance area under the ceramic resonator in the inner layers also i.e. layers 2, 3 & 4, or is it sufficient if we just clear the GND plane in the top layer?

2. Is it recommended to place GND stitching vias around the tesonator (green dots as shown in below image) or should we completely avoid any vias around the resonator?

Answer 1

You can clear the copper under it on all layers. The hole this leaves is quite small, I doubt it would have any effect. The ground stitching around the area is a little bit like a shield. They don't want any fields developing across the gap which might interfere with the resonator. Personally I would use the vias but skip every other one, I don't think you need that many.

Answer 2

It's always a nice idea to consult with your vendor when you see some "non-standard" recommendations. However, regarding pour cutout, I may suggest two possible reasons for such recommendation:

1. It reduces stray capacitance, which affects your load capacitance (and shifts the fundamental harmonic)
2. It is a general recommendation to avoid newbies' mistakes, like a noisy trace under a crystal oscillator

For the first case, the most critical will be tightly coupled layers (in a standard 4L PCB, it'll be the next one below your oscillator). And I had such an issue before. When I redesigned the 2L board into 4L, there was a frequency shift of about 20 ppm, and it was corrected with a pour cutout under the oscillator (second way - to lower your load caps, wasn't good in my case due to supply chain).

If you wish to learn more about stray capacitance and how it affects - AN2867 application note from the ST is what you need.

Everything is even more straightforward regarding vias - this thing is called "via fence" or "guard trace," depending on the context. Various articles can read about it, but unless we're talking about RF, these structures generally make sense on a 2-layer board because of the poorly coupled reference plane (unless your PCB is 0.2mm thick). I hadn't met any evidence it makes sense for multilayer ones. However, it won't make your design operate worse, especially if you run with pour cutouts under the oscillator.