I understand that Preset and Clear inputs are asynchronous inputs which means whenever Clock signal is low one of them can immediately set the output to 1 (Preset) or to 0 (Clear) (assuming they are active high inputs). But I wonder what happens when one of those inputs has been set to 1 when Clock was 0 and then Clock goes 1. Does J and K ovewrite Preset/Clear or they have to be released to let J and K affect the output?
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\$\begingroup\$ The CLK signal is an input to both of the front two NAND gates and so the effect takes place only after CLK is asserted. \$\endgroup\$– AlfroJang80Commented Jul 4, 2019 at 23:27
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1 Answer
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If Preset and Clear are asynchronous, they will be effective regardless of the state of the clock.
If you set "Clear" active, the flip-flop will be cleared immediately regardless of the state of the clock, and will remain clear if the clock changes while Clear is held active.
A synchronous Set or Clear will only set or clear the flip-flop on an appropriate clock edge.
answered Jul 4, 2019 at 22:49
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\$\begingroup\$ Thank you for the answer. Please find my attachment. I think my confusion comes from the part: 'The inputs only affect the circuit when Ck=0 (i.e. asynchronously)'. When they say 'asynchronously' I understant it refers only to Preset and Clear as they described J and K inputs as synchronous (and there is Ck input on the schematic). drive.google.com/open?id=1DCUri1puWMd-FxgPzyaLFrIa4NmqTrFB \$\endgroup\$– ArniCommented Jul 4, 2019 at 23:23
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\$\begingroup\$ please put the link to the document into its proper place, in your question above ... all of this comment pertains to the question and should have been there from the begining \$\endgroup\$– jsotolaCommented Jul 5, 2019 at 0:40
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\$\begingroup\$ @Arni: Unlike your example, in a Real JK flip-flop like the 74LS76, the preset and clear inputs affect the state at any time, regardless of he clock. (Not that your example is wrong - there are many ways to build these things, and different designs may operate differently.) \$\endgroup\$ Commented Jul 5, 2019 at 0:42
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\$\begingroup\$ I have added the photo of the whole page \$\endgroup\$– ArniCommented Jul 6, 2019 at 19:53