I'm designing a battery charging circuit for a portable device. Conceptually it looks lik so:


simulate this circuit – Schematic created using CircuitLab

As a safety function, the circuit can be interrupted by the transistor, thus interrupting the battery charging process. What leads me to write this post is that I need a transistor design that is normally closed (battery is normally charging). However, if a problem is detected, an MCU would send a control signal to it in order to open the circuit and stop the charging process.

My questions in conclusion are:

  1. What kind of transistor should I use? A depletion P-Channel Mosfet? If so, how would the circuit look like?
  2. Could this be accomplished with a normal P-Channel Mosfet (normally open unless activated) with some additional circuitry?

Thank you very much for your time and help!

  • \$\begingroup\$ What voltage is Vcc? \$\endgroup\$ – Huisman Jul 5 '19 at 11:30
  • \$\begingroup\$ @Huisman Sorry for not saying that. Vcc is 10V. \$\endgroup\$ – Sergi MF Jul 5 '19 at 11:48
  • \$\begingroup\$ Depleation MOSFET comes to mind, but normal procedure would be to have an auxilary circuit to either pull down the gate for a P-MOSFET (enhancement) or pump gate voltage above Vcc for a N-MOSFET (again enhancement). \$\endgroup\$ – winny Jul 5 '19 at 11:48
  • \$\begingroup\$ this is a very poorly designed spec and answer. you must avoid high linear and switching losses by using a SMPS buck boost high efficiency design. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 5 '19 at 17:35
  • \$\begingroup\$ @SunnyskyguyEE75 could you please elaborate on your comment? How does a SMPS buck-boost fit into my design? Thanks in advance \$\endgroup\$ – Sergi MF Jul 8 '19 at 8:06

You were almost there!
You can indeed use a PMOS keeping in mind the ratings (regarding VDS and IDS). It should be oriented like you drew it: the body diode is reversed biased.
To turn on the PMOS, you need a lower voltage than Vcc on the gate of M2. This is achieved by adding resistor R1 (and R2) and a N-channel mosfet M1 which pulls the gate of M2 to the right VGS voltage when M1 is turned on by the uP.
R3 ensures M1 is turned off by default and therefore M2 is also turned off by default, unless the microprocessor turns the Control signal high.

In case of Vcc being lower than 15V, you can leave out R2. In case of Vcc higher than that, you should take care the VGS of M2 doesn't exceed -20 V (which applies for most mosfets, check the datasheet of your selected PMOS). R1 and R2 should make a voltage divider such that M2 is decently turned on (which is typically quite a bit higher than VGS(th)!) So, in that case recalculate the values of R1 and R2 in that case.

I initially understood the mosfet M2 should be turned off when the Control signal was logic low. It has to be the otherway around.
By default / when the Control Signal is 0V, M3 is not conducting and therefore the current through R4 turns on Q1. Q1 one pulls the gate of M2 low and therefore turns on M2.
When a logic high signal is applied as Control Signal, mosfet M3 shorts the base of Q1 to ground. Q1 stops conduction and M2 turns off.


simulate this circuit – Schematic created using CircuitLab

| improve this answer | |
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    \$\begingroup\$ I think this is just the opposite of what the OP asked for...M2 needs to be conducting by default, not off by default. \$\endgroup\$ – Elliot Alderson Jul 5 '19 at 12:05
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    \$\begingroup\$ Yes. It will, because I assumed the detecting and protection uP is on by default as well! If the uP fails its duty due to e.g. power cutt, M2 will be still turned off. \$\endgroup\$ – Huisman Jul 5 '19 at 12:19
  • \$\begingroup\$ @Huisman when no signal (0V) is being applied to M1's gate, is M2 conducting then (closed circuit)? Maybe I wasn't clear before. What I need is that with no input from the MCU at M1, M2 should conduct, be closed, by default \$\endgroup\$ – Sergi MF Jul 5 '19 at 12:32
  • \$\begingroup\$ @SergiMF When no signal (0V) is being applied to M1's gate, M2 is not conducting (open circuit), a high signal on M1's gate turns on M2. I think this is the safest. But if I understand well, it should be the opposite: a high signal from the uP should turn M2 off. Unfortunattely I'm not able right now to change the circuit right now, will do it asap. \$\endgroup\$ – Huisman Jul 5 '19 at 13:04
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    \$\begingroup\$ @SergiMF Please find the modified circuit. My apologies for my misunderstanding. Good luck with your project! \$\endgroup\$ – Huisman Jul 5 '19 at 15:37

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