Is it possible to detect a keypress on a PS/2 keyboard connected to an FPGA, using VHDL, with only PS/2 clock signal?
library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; entity Keyboard_Drive is Port ( PS2_DAT, PS2_CLK, clk, rstn : in std_logic; end entity; architecture rtl of Keyboard_Drive is signal PS2_CLK2, PS2_CLK2_old, PS2_DAT2, detected_fall : std_logic; signal shiftreg: std_logic_vector (9 downto 0); signal pressed: std_logic := '0'; begin input_signals : process (clk) begin if rising_edge (clk) then -- get data PS2_DAT2 <= PS2_DAT; PS2_CLK2 <= PS2_CLK; PS2_CLK2_old <= PS2_CLK2; end if; end process; detected_fall <= (NOT PS2_CLK2) AND PS2_CLK2_old; Key: process (clk, rstn) begin if rstn = '0' then shiftreg <= (others => '0'); elsif rising_edge (clk) then -- assign shift if detected_fall = '1' then shiftreg (8 downto 0) <= shiftreg (9 downto 1); shiftreg (9) <= PS2_DAT2; end if; end if; end process;
I was considering to add this process (code under) to try to detect only when PS2_CLK rises, because I read that PS2_CLK is constantly high (PS2_CLK=1) when they keyboard is not in use.
sound : process (clk) is begin if rising_edge(PS2_CLK2) then pressed <= '1'; else pressed <= '0'; end if; end process;
But this gives an error ('couldn't implement registers for assignments on this clock edge').
I have tried to read and understand bouncing and de-bouncing and how to take it into consideration. I have tried many solutions and many hours. It felt as a simple problem in the beginning but it never gets solved.
The pressed signal has to be a steady '1' when being pressed since the signal will be used for producing sound when being pressed.
Thanks in advance.