I'm learning Verilog with some background in VHDL and C. I would like to know if Verilog if blocks are executed concurrently or not, and if this is IDE- or vendor-dependent.
For example, are the following always equivalent or never equivalent, or sometimes equivalent, depending on something I'm not aware of?
always @ (posedge clk) begin if (x == 1'b1) begin // do something end // possibly other code if (y == 1'b1) begin // do something else end // possibly other code end
always @ (posedge clk) begin if (y == 1'b1) begin // do something else end // possibly other code if (x == 1'b1) begin // do something end // possibly other code end
The if blocks and the "// possibly other code" chunks of code always execute sequentially, correct? My understanding is that the two blocks above should never be the same in Verilog because the line-by-line sequence is different.
I've read that "statements in procedural blocks are executed sequentially", implying that the code should be synthesized to execute in hardware line-by-line. However it is unclear to me if the blocks themselves are processed sequentially, and simulating with just one behavioral simulator doesn't address the question of how universal Verilog synthesis is supposed to be.