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This question might seem very basic, but it will help me a lot if someone can answer it from the basics!

I have just finished my first year at college and there was a course on digital design, where we studied the fundamentals of digital systems and also implemented various circuits using ICs in the lab.

When we saw the IC in class, we just focussed on the circuit inside the IC - how everything is connected and what logic gates/ FFs are used. But while implementing circuits in lab, I saw that there were 2 power pins also, on each IC.

Why do they need power pins? Like, all that is present in the IC is a few logic gates (even FFs are logic gates at a very fundamental level) right? Logic gates do not require power when we have to use them right?

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    \$\begingroup\$ Where do you get the idea that logic gates don't require power? \$\endgroup\$ – Hearth Jul 7 '19 at 2:45
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    \$\begingroup\$ I wish logic gates didn't require power. Imagine the data processing we could do! \$\endgroup\$ – DKNguyen Jul 7 '19 at 2:51
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    \$\begingroup\$ were you paying attention when you were implementing circuits in the lab? ... it seems that you nay have somehow missed an important part of the lab ... what were these circuits in the lab? \$\endgroup\$ – jsotola Jul 7 '19 at 3:14
  • \$\begingroup\$ fundamentally, the electric-fields between all the wiring will store charge. As logic levels change, charges move, and in general the charge is wasted, and is not recycled. Thus the VDD/GND must provide new charge. \$\endgroup\$ – analogsystemsrf Jul 7 '19 at 16:27
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Why do they need power pins? Like, all that is present in the IC is a few logic gates (even FFs are logic gates at a very fundamental level) right?

schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Equivalent circuit for the simplified output stage of a CMOS logic gate. As shown in the switch version the output is pulled high. All the other transistors in the gate will also require power connections.

They need power pins because the digital logic needs to supply power from the positive rail to create a logic 1 or sink power to the ground rail to create a logic zero.

Logic gates do not require power when we have to use them right?

Without power connections there could be no pull high or pull low. Logic gates do not source or sink electrical current from nowhere. It has to come from and return to the supply.

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First things first. Some ICs do consume power even if they are not doing anything, check Diode logic and transistor-transistor logic ICs (1) (2).

Secondly. The power pins are not only used for "power". They are also used for ESD protection. So if one of the inputs were to be higher than they were supposed to, it will get "shorted" to the power supplies. Link (3) "shows" a simple ESD protection circuit/diode. [This is the reason you might be able to use your ICs even though there is no power; it is because your inputs are "powering" the power supplies ]

Thirdly. Vdd and Vss [or Vcc and Vee for TTL ICs] set your noise margins. Therefore, You need a constant voltage reference to tell what is a logic low or a logic high, even if you do not draw any current!

(1): https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic

(2): https://en.wikipedia.org/wiki/Diode_logic

(3): https://en.wikipedia.org/wiki/Transient-voltage-suppression_diode

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  • \$\begingroup\$ Thanks a lot! The links you provided were helpful! \$\endgroup\$ – Akilesh Kannan Jul 7 '19 at 3:29
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Digital logic needs a reference voltage for ‘1’ and for ‘0’.

Take the simplest logic element: the inverter. In CMOS it is a complementary pair - a P-channel and N-channel FET, with the sources and gates tied together. The P-channel source goes to a power so that it can drive a ‘1’ on its drain when it is turned on; likewise the N-FET has its source tied to GND so that it can drive a ‘0’.

If the pair is driving an open circuit they in theory don’t use power (and some CMOS ICs come very close.) Nevertheless they need that ‘1’ and ‘0’ reference to do their job, and in the real world they’ll use some power just charging and discharging the capacitance on the signal they’re driving. In fact the power calculation is proportional to both the switching frequency and the capacitance - called ‘dynamic’ or ‘switching’ power.

More about that here: http://www.ti.com/lit/an/scaa035b/scaa035b.pdf

Also, FET pairs aren’t perfect - they don’t turn off completely. That inverter will have some leakage current through the ‘off’ device that isn’t really fully off. This depends on the threshold voltage of the transistor. But there’s a trade off: the lower the threshold, the faster the switch.

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The voltages and the currents the logic gates work come from an external source (the power supply connected to power pins), the voltages and currents do not magically exist or are generated at the logic gate.

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