Lets say we want to create a generic t flip flop counter, the structure of this kind of counter is perfectly repetitive, and you can synthesize one with arbitrary length just using a
however the bound for that
for and the length of the output is internal to the file, a constant, is there a way to sort of passing an argument when creating a component so as to define the length of the counter when creating the component instead of in the file?
here is the code of the counter i made
library IEEE; use IEEE.STD_LOGIC_1164.ALL; use ieee.numeric_std.all; entity counterTst is port( enable: in STD_LOGIC; clk: in STD_LOGIC; rst: in STD_LOGIC; output: out STD_LOGIC_VECTOR(3 downto 0) ); end counterTst; architecture rtl of counterTst is constant COUNTER_LEN: integer := 4; component t_ff is port( rst: in STD_LOGIC; clk: in STD_LOGIC; inp: in STD_LOGIC; t: out STD_LOGIC ); end component t_ff; signal tin: STD_LOGIC_VECTOR(COUNTER_LEN-2 downto 0); signal tout: STD_LOGIC_VECTOR(COUNTER_LEN-1 downto 0); begin T_CHAIN_GEN: for i in 0 to COUNTER_LEN-1 generate START_POS: if i = 0 generate FF0: t_ff port map(rst, clk, enable, tout(0)); end generate START_POS; POS_1: if i = 1 generate tin(0) <= tout(0) and enable; FF1: t_ff port map(rst, clk, tin(0), tout(1)); end generate POS_2; POS_N: if i > 1 generate tin(i-1) <= tout(i-1) and tin(i-2); FFX: t_ff port map(rst, clk, tin(i-1), tout(i)); end generate POS_N; end generate T_CHAIN_GEN; output <= tout; end rtl;