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I'm so confused about beq function in assembly MIPS.
Lets assume I have beq $t1 $t2 60 , so it would be mapped as I type function. so we could say for example assuming that beq mapped to

100100 , $t1=5 , $t2=4, and immediate 60

so the block of IP type instruction is:

100100 | 5 | 4 | 60

but what's confused me that beq means if $t1 = $t2 then it would jump 60 steps from the offset PC .. so the I type instruction should be mapped to 100100 | 5 | 5 | 60 so the implementation mapping of registers should be 5 and 5 .. not 5 and 4 , am I right? because beq means $t1=$t2 ...so must the mapping instruction of registers of that instruction must be

100100 | 5 | 5 | 60 and not
100100 | 5 | 4 | 60

so what should that instruction mapped?

to 100100 | 5 | 4 | 60
or to 100100 | 5 | 5 | 60 ?

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  • \$\begingroup\$ Why do you think "so the I type instruction should be mapped to 100100 | 5 | 5 | 60"? \$\endgroup\$ – the busybee Aug 29 '19 at 6:24
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The numbers for rs and rt are the indexes of the GPRs to compare. The values stored in these registers are to be compared.

For your example with some exemplary values: If R5 contains the value 23 and R4 the value 42, the branch will not be taken. But if R4 holds also the value 23, the branch will be taken.

Note: Since I don't use MIPS regularly I might be wrong. But 100100 is the opcode for lbu, isn't it? I found 000100 as the opcode for beq.

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