# Verilog Reg File: Cant mix blocking and non-blocking assigment

I want to implement a blocking read to read the data as soon as it is written. I am trying to implement a MIPS 1 pipeline and i need the data to be available in the same clock it is written. The flips flops for intermediate variables between different stages work on positive clock edge. The write is on the negative clock edge. If I want to read on a negative or positive i'll have to wait to the next cycle. I am trying to write on the first half of the cycle and read on the second half. But if i read on the positive the FFs from the next stage won't get the value.

module registers#(
)(
input clk,
input reset,
input regwrite,
input [4 : 0] wr,
input [4 : 0] rr1,
input [4 : 0] rr2,
input [31 : 0] wd,
output[31 : 0] rd1,
output[31 : 0] rd2
);

reg [31 : 0] registers [31 : 0];

integer i;
initial
begin
for(i = 0; i < 32; i = i + 1)
registers[i] = 0;
end

assign rd1 = registers[rr1];
assign rd2 = registers[rr2];

always@(negedge clk)
begin
if(reset)
begin
for(i = 0; i < 32; i = i + 1)
registers[i] = 0;
end
else
begin
if(regwrite)
registers[wr] <= wd;
end
end

endmodule


Ok i fixed it...

Turns out the error message was from a typo.

I changed:

if(reset)
begin
for(i = 0; i < 32; i = i + 1)
registers[i] = 0;
end


To:

if(reset)
begin
for(i = 0; i < 32; i = i + 1)
registers[i] <= 0;
end