why do we need pre-post amble for READ or WRITE DQS ?

1 ) one reason could be --> Because transitions of voltages from logic level 0 to 1 or 1 to 0 take time to complete: so the strobe is asserted a suitable time after the start of data lines transitions to tell the reader that the data is valid in the sense that the transitions between logic levels on the lines have been completed.

---------- but there is DQS to do this job....then why extra pre and post amble ?


DQS is a bidirectional, 3-state signal that is also a primary timing reference for its corresponding data lane. It needs that extra preamble time to establish its phase alignment for the DLL (that is, ‘train’ the DLL) so that the data following can be sampled properly with the best timing margin.

The postamble is used to ensure a smooth hand-off between read and write transactions, that is, to allow turn-around time so the host and DDR device don’t clash with each other in a way that generates a false edge on DQS.

Micron application note TN 46-05 explains in more detail.

  • \$\begingroup\$ Delaying the incoming strobe for READs is more involved and will be covered in detail in an independent technical note. <-- Do you have idea on which exact independent technical note it is referring to ? I suppose for READ preamble, DQS is aligned with DQ , so why need to delay the incoming DQS strobe ? \$\endgroup\$ – kevin998x Feb 21 at 14:31
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    \$\begingroup\$ The launched DQS from the host is center aligned with DQ, so the DRAM uses it directly. The DRAM launches DQ and DQS together, so the host has to delay DQS to center-align it with DQ. That’s what the DLL does, and part of DRAM initialization is ‘training’ the DLL to get the best sampling margin on DQ. Take a look at the Xilinx or Altera DRAM IP appnotes to get an idea of that process. \$\endgroup\$ – hacktastical Feb 21 at 20:26
  • \$\begingroup\$ As far as Micron, they don’t do controllers so it’s unsurprising they don’t have an appnote that covers it. \$\endgroup\$ – hacktastical Feb 21 at 20:33

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