Recently, I studied dvfs tables for 3 SOCs: exynos8890(LITTLE cluster), exynos7880, snapdragon 625.

Here is the result: octave source code

CPU power versus frequency

The point is, that different SOCs with pretty same manufacturing process (14nm), same CPU architecture (arm53), but different manufactures, and consumer grade have different voltage at given frequency.

It's clear, that reducing CPU power voltage, one can reduce dynamic consumption, but still,

Does reducing CPU power voltage has any drawbacks on overall CPU power consumption?
Also, why exynos8890 has peak voltage at 1.6GHz, but not at MAX frequency?

  • \$\begingroup\$ There's a lot more to the design of an FET than just the process size, but you also have to consider that even identical silicon might lead to different recommendations when passed through two different organizations. This question is far too broad to fit within the Stack Exchange requirement for answerable specificity. \$\endgroup\$ Jul 10, 2019 at 15:46
  • 2
    \$\begingroup\$ @dzmitry do you have to put that graph in uV? Volts is more common \$\endgroup\$
    – Voltage Spike
    Jul 10, 2019 at 15:47
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    \$\begingroup\$ I don't think the same "14nm process" is actually the same process between different manufacturers or foundries. Why would they share their process? \$\endgroup\$
    – DKNguyen
    Jul 10, 2019 at 16:31
  • \$\begingroup\$ For the same "marketing 14nm (or whatever) process" every silicon FAB offers tree or four (or more) cell libraries with different power/speed optimizations, low-power low-speed library, high-power high performance libraries, etc. So the results will all differ. \$\endgroup\$ Aug 25, 2019 at 21:45

1 Answer 1


There are two kinds of power losses in a chip:

  • static (leakage)
  • dynamic (switching)

Voltage scaling reduces both power losses as a square of the voltage so the benefit of reduced voltage is substantial, especially for a mobile device where battery life is king.

There is a trade off however. Generally, a lower voltage results in a longer switching time for MOS logic, so it requires reducing the clock rate too. This has an upside in that it reduces dynamic power as a linear function of clock rate.

(The power relationship between voltage, frequency, and capacitance is W=V^2 * f * C, where C is the sum of capacitance on driven signals.)

Now, why the differences at the same process node? Different designers will use different strategies to meet timing in their parts. One such strategy is to use low-threshold (low-Vt) transistors in certain critical paths. This comes at a price however: increased leakage power.

So even within the same company (Samsung in this case) and on the same process, you will see differences. Some parts are optimized for performance, others for power. A performance-oriented part that uses low-Vt paths more generously will use more power at a given frequency and voltage, but will be ultimately faster at a given voltage.

The reason for the odd dip for Exynos 8890 may just be that’s the power profiles they were able to test.

  • \$\begingroup\$ Note that depending which voltage was measured (and how), the odd dip might just be V droop. \$\endgroup\$
    – Turbo J
    Jul 10, 2019 at 17:39

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