There are two kinds of power losses in a chip:
- static (leakage)
- dynamic (switching)
Voltage scaling reduces both power losses as a square of the voltage so the benefit of reduced voltage is substantial, especially for a mobile device where battery life is king.
There is a trade off however. Generally, a lower voltage results in a longer switching time for MOS logic, so it requires reducing the clock rate too. This has an upside in that it reduces dynamic power as a linear function of clock rate.
(The power relationship between voltage, frequency, and capacitance is W=V^2 * f * C, where C is the sum of capacitance on driven signals.)
Now, why the differences at the same process node? Different designers will use different strategies to meet timing in their parts. One such strategy is to use low-threshold (low-Vt) transistors in certain critical paths. This comes at a price however: increased leakage power.
So even within the same company (Samsung in this case) and on the same process, you will see differences. Some parts are optimized for performance, others for power. A performance-oriented part that uses low-Vt paths more generously will use more power at a given frequency and voltage, but will be ultimately faster at a given voltage.
The reason for the odd dip for Exynos 8890 may just be that’s the power profiles they were able to test.
