I'm trying to simulate the parasitic insensitive switched capacitor circuit shown here: enter image description here

I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using non-overlapping clocks with period 1us and pulse width 0.4 us. Both caps are 1pF. The schematic is shown below:

enter image description here

The opamp is generated using a vcvs with open-loop gain 1e20.

However, the output of my integrator seems to have a huge unexpected gain, instead of the predicted gain of 1. (Check out the swing in the next image). It also has some strange offset.

enter image description here

Does anyone know where I am going wrong with my simulation? Thanks.

  • \$\begingroup\$ Which component is the VCVS? \$\endgroup\$ – Voltage Spike Jul 13 '19 at 22:07
  • \$\begingroup\$ Voltage controlled voltage source from the analoglib. It can act as an opamp if your gain is very high. \$\endgroup\$ – Sidharth Thomas Jul 15 '19 at 2:10
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    \$\begingroup\$ I know what a VCVS is, which designator is the VCVS? Are you talking about the opamp? I've never heard of an VCVS having open loop gain \$\endgroup\$ – Voltage Spike Jul 15 '19 at 4:30

Some things to try:

To solve the offset problem try putting a large resistor to ground on the input of the VCVS, like 1e12 or larger. That way the simulation can find the DC operating point on startup.

To solve the gain issue, use an actual integrator with resistors enter image description here


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