I am using cadence virtuoso. My input is a sine wave of 1 V amplitude, 0 DC and 1 kHz frequency. I am using non-overlapping clocks with period 1us and pulse width 0.4 us. Both caps are 1pF. The schematic is shown below:
The opamp is generated using a vcvs with open-loop gain 1e20.
However, the output of my integrator seems to have a huge unexpected gain, instead of the predicted gain of 1. (Check out the swing in the next image). It also has some strange offset.
Does anyone know where I am going wrong with my simulation? Thanks.