# How to specify a value for each bit of the reg in Verilog?

I want to declare a reg of 8 bits and set the value for each one of the bits separately (based on another "counter" reg) inside an always block using Verilog.

Here is what I thought:

module readvalue (
button_1,
button_2,
value,
counter);

input button_1;
input button_2;
output value;
output counter;
reg [7:0] value;
reg [7:0] counter = 8'd0;
always@(posedge button_1 or posedge button_2)
begin
if(button_1)
begin
[counter]value <= 1'b0;
counter <= counter + 8'd1;
end
else if(button_2)
begin
[counter]value <= 1'b1;
counter <= counter + 8'd1;
end
end
endmodule


The idea behind the code is that when button_1 is pressed, 1 is stored in a particular bit of value and when button_2 is pressed, 0 is stored. I have a higher module in the hierarchy to make readvalue stop when counter is equal to 8 in decimal.

The code, as expected, gives me the following errors:

Error (10170): Verilog HDL syntax error at calculator.v(17) near text: "[";  expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.

Error (10170): Verilog HDL syntax error at calculator.v(22) near text: "[";  expecting "end". Check for and fix any syntax errors that appear immediately before or at the specified keyword. The Intel FPGA Knowledge Database contains many articles with specific details on how to resolve this error. Visit the Knowledge Database at https://www.altera.com/support/support-resources/knowledge-base/search.html and search for this specific error message number.


How can we put it to work?

I am using Intel's Quartus Premium Lite Edition 18.1 (with the latest update pack) on Ubuntu 18.04 with the default configuration. If I have not been clear or you need more information, just comment and I will provide.

I am a beginner on Verilog so, sorry for such a simple doubt.

EDIT 1: button_1 and button_2 are never going to have a posedge at the same time (or even in the same second) in my implementation.

First, you need to put the index after the register name, like

value[counter]


not

[counter]value


However, I'm not sure if using a variable as an index into a register will be simulable and synthesizable.

If not, you could use something like

always@(posedge button_1 or posedge button_2)
begin
if(button_1)
begin
value <= value & ~(8'b1 << counter);
counter <= counter + 8'd1;
end
else if(button_2)
begin
value <= value | (8'b1 << counter);
counter <= counter + 8'd1;
end
end


However you should also be aware that this is likely not synthesizable because you are trying to make logic that is edge-sensitive to two different signals and if you consider all the subtleties, the actual logic in your FPGA or CPLD doesn't do that. You can probably make an SR latch, but that doesn't work exactly like your code because it will behave differently if, for example, button_1 is still asserted when the rising edge of button_2 arrives.

The usual way to code these things for an FPGA is to have a clock available that runs much faster than you expect button_1 and button_2 events to arrive, and use that to clock logic that detects edges on the input signals and responds to them.

For example (sorry, code not tested),

reg b1d; b2d; // delayed button signals

always @(posedge clk) begin
b1d <= button_1;   // Notice: non-blocking assignment
b2d <= button_2;
if (button_1 & ~b1d) begin
// A rising edge on button 1 happened
// ...
end
else if (button_2 & ~b2d) begin
// ...
end
end

• Thanks for your reply! I will test your codes as soon as possible and give a better feedback. In any way, just to clarify, button_1 and button_2 are never going to have a posedge at the same time (or even in the same second) in my implementation. I will add this to the question. But I understood what you meant. – Cooper Jul 11 '19 at 1:48