Pipeline and real parallelism?

Question

I have read several articles which say that the CPU has the ALU (and other small specific execution units), Control Unit and the Registers and well other buffers/pipelines, internal buses etc.

The Control unit:

The control unit implements the architecture of the CPU. It performs the tasks of fetching, decoding, managing execution and then storing results.

Studying pipeline concept, and what I understand is that at least two steps:

1. Fetch,Decode--->CONTROL UNIT

2. Execute-------->ALU and OTHER EXECUTE UNITS

Both steps PERFORMED IN PARALLEL. That is, while the CPU is executing an instruction, at that same time another is being fetched and decoded.

Am I correct in assuming the above? Or do the Control unit and Execution unit work one after the other like some kind of switching between clock cycles?

Answer 1

Yes. This is the exactly benefit in use a pipeline. The most simple real life example is a laundry.

When you just arrive there, you have dirty clothes that you want to "process". You put the first group of clothes inside the washer and wait until it finishes. When it is ready, you get your first pack of clothes and put all in the dryer machine and fetch and load more clothes into the washer in parallel. When the dryer end its job you then start the "folding cycle", releasing the dryer.

I think you get the idea that while you are folding you can load more clothes in the washer and dry more clothes from the washer in parallel.

The main idea in both cases, processor and laundry, are similar: you can do more in less time by doing parallel jobs.

In the opposite, a processor without a pipeline have to wait all the execution ends to fetch another instruction. Using the laundry analogy again, it is like you only start to wash another group of clothes only after fold all clothes from the first group, wasting time in the middle.

Answer 2

Yes, in a hardware pipeline, all of the steps are happening in parallel.

Answer 3

http://en.wikipedia.org/w/index.php?title=File:Intel_Core2_arch.svg&page=1

Actually there are both series & parallel operations in a pipe to maintain cache concurrency and pre-fetch and pre-decode instructions on a 128 bit bus. The depth of each level of bus including 2 levels of cache, as it gets deeper, adds to latency, but also improved access time when frequently accessed from cache (called cache hits). When an object is locked to an I/O and another thread wants to access the same object, resource management either blocks permissions to write requests or locks the object until free. Cache size increases permit this frequent occurrence to be delayed less for parallel operations by adding serial delay or re-ordering requests, when it is not shareable. If you watch windows code execute using procmon.exe, many poorly written programs will experience fast i/o failure followed by normal I/O success. (not just windows)

Parallel cores must be managed with segregated threads to avoid concurrent lock-outs.