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I have made a half bridge inverter, in the lab and on simulation software. I have used the gate drive IR2110a and am supplying it with a square wave pulse and it is then applying the gate voltage to the high and low side MOSFETs (ho and lo on the diagram).

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I have found that using a purely inductive load of 100uH causes the circuit to not work as expected, as the Vs (which should be a square wave) massively droops and therefore the Vho is too small to turn on the high side MOSFET for the normal time expected. Shown below:

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Increasing the value of the inductance reduces this droop but there are still sloping tops on the Vs waveforms. The current in the inductor, I(L1), also becomes the expected triangular wave rather than the more curved wave found above.

enter image description here

Can anyone explain in terms of what is happening in the circuit why the droop happens? and also why the current in the inductor looks as it does in the first set of graphs?

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  • \$\begingroup\$ The HO and LO FET drivers have RdsOn which limits the current to some value, within which dI/dt is limited by V/L then the sag is limited by I/C=dV/dt \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 12 '19 at 14:01
  • \$\begingroup\$ X(L(f)) = 2pi*fL and I=V/(R+jX(f)) so NO the steady state or target current increases with lower impedance but rise time increases with L/R so it takes longer time to reach constant current. using a lower f, allows more current but also more ripple. Using a larger L/C also reduces resonant frequency. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 12 '19 at 14:19
  • \$\begingroup\$ First you define specs of current, resonant frequency and voltage then purpose of real load impedance then choose RLC values with losses and response desired. \$\endgroup\$ – Tony Stewart Sunnyskyguy EE75 Jul 12 '19 at 14:20
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First, one misconception to clear up. You said:

as the Vs (which should be a square wave) massively droops and therefore the Vho is too small to turn on the high side MOSFET for the normal time expected.

However, you have a boot-strapped driver. It maintains a Vgs of about 15V (from VCC) at the gate. If you plotted both v(ho) and v(s) on the same graph, or (v(ho) - v(s)), you'll see the 15V is maintained when the gate is supposed to be on. Put another way, v(ho) looks weird because v(s) looks weird.

Which gets to the first problem with the 100µH inductor simulation: your currents (i(L)) vastly exceed what C1 and C3 can supply to keep v(va) near mid Vrail. Take a look at v(va) and it'll probably be swinging wildly around.

The second problem, which Tony mentioned, is the Rdson of your MOSFET. Looking at the part datasheet, it looks like it is about 0.25Ω nominal. Based on your inductor currents, it's one of the culprits for the crazy v(s) waveform. 50A at 0.25Ω Rdson gives 12.5V drain-source drop, which is dangerously approaching saturation in this device. The Rdson also explains what you call "droop" in the second simulation.

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