# How can output from a single logic gate/DIP switch supply input for multiple gates?

I have googled this quite profusely, and can't seem to find a straight answer. I am a consummate newb when it comes to electronics, so please forgive my ignorance.

I am wondering how it is possible to send approx. 5V* to more than one logic gate simultaneously from the single output (1-bit) of a previous gate and/or dip-switch, assuming one was to build the system physically on a breadboard.

I have just figured out in my head and on paper how to make a very basic adder work, with the help of this site.

The problem, if I'm remembering my high school science teacher correctly, is:

The only way to "double-up" a voltage to 10V (to supply 2 gates with 5V "1" each) would be to run the original 5V signal in parallel, rather than splicing/forking (which, I believe, would be in series, not parallel), which would halve it to ~2.5V (not sure on that, just my memory of how electronic systems were explained back then).

For the adder, you have to send the "A-bit #1" to two different gates from a single dip-switch. Can someone please explain (physically and in terms of voltage) how this is possible. This is not for homework, simply for my own edification/hobby. Thanks in advance for your answers.

If necessary, I can upload my diagrams (on paper).

*Assuming 5V is the "standard" HIGH voltage i.e. "1" for this type of system, as per the article, and that ~0V is LOW voltage, i.e. "0".

• A very warm welcome to the site. I think you're confusing voltage with current in thinking that the source gate output must provide the sum total that the load gate inputs draw. Each load gate input will recognise the same output voltage from your single source gate (unless wildly overloaded by gates). Each input will draw some current, which will be tiny compared to your source gate's drive capability e.g. it can provide lots of mA and the inputs draw a few uA, assuming you're using HC/HCT (mid-1980's) or newer. Some more reading to do through Google I think, tons of info' on this there :-) – TonyM Jul 12 at 21:22
• Thank you, TonyM. So, physically, you would simply fork (sheathed) copper wire from the output of the source gate into 2 "branches", and attach 1 branch each to the two destination gates? – Brandon G Jul 12 at 21:26
• Yes, exactly. Each load gate input has a single (wire) connection to the same source gate output. – TonyM Jul 12 at 21:39
• Most logic gate inputs are high impedance, so one output can supply enough current for several inputs. – zeta-band Jul 12 at 22:16

Remember that voltage is like pressure in a pipe. If the flow from two different pipes is combined, there is more flow, not more pressure.

Same thing applies when connecting two 5V supplies or signals together, there is more current when paralleling.

If you want more voltage, you need a charge pump or DC to DC converter.

An Add gate compares the voltages, if both are high at 5V, it wouldn't be possible in the circuit world with switches to get 10V. So instead the additional information is carried as another signal line called the carry out line:

• There is a limit to how many inputs you can attach to the output of a gate, but it's not the reason you're thinking. In the old days of TTL logic, each gate input consumed some current, and if you attached too many to one output it couldn't drive it (think of plugging too many lights into one circuit). With CMOS logic each gate input doesn't consume current just sitting there, but it does need current to change from one voltage to another (because there's some capacitance) -- so if you hang too many gates onto an output, then it'll slow it down too much. – TimWescott Jul 12 at 23:49

EDIT: tl; dr version: Here's someone who built this on proto board. Have a look: http://egomachines.com/animoid/ann-hardware/build-full-adder.html

Now, more discussion:

First, gates don't literally 'add' voltages together (op-amps can, but that's another disussion.) Rather, they use voltages to represent numbers as binary digits, or bits.

So a 1-bit full adder implements the function a + b + c = sum, with a carry-out bit. In binary notation then,

a    b    c  = carry,sum
-------------------
0b + 0b + 0b = 0,0b
0b + 1b + 0b = 0,1b
1b + 0b + 0b = 0,1b
1b + 1b + 0b = 1,0b
0b + 0b + 1b = 0,1b
0b + 1b + 1b = 1,0b
1b + 0b + 1b = 1,0b
1b + 1b + 1b = 1,1b


You have three 0/5V inputs a, b and c that map to two 0/5V outputs, sum and carry that you will see below.

Back to gates now. Gates have four kinds of connections:

• Input
• Output
• Power
• Ground

Normal logic diagrams don't show the power connections. In the real world, when you make a logic circuit using ICs, the first thing you need is to make sure they have their power connections (+5 and GND) tied.

Once you've done that, then connect your inputs, your outputs, and your outputs that connect to other inputs.

If you have a gate output feeding another gate input, it's perfectly fine to tie them output-to-input. And, importantly, a single gate output can drive multiple gate inputs just by tying them directly. This is called fanout and is supported by TTL (74xx) and CMOS (74Cxx, CD4xxx) type logic.

Below is a diagram showing a full-adder connected from individual gates:

This shows the common power connections, and how the gate inputs and outputs tie together, including the driving-multiple-input fanout connections.

Conveniently, this circuit includes LEDs to show the state of sum and carry. That’s another thing that gates can do: provide current to drive stuff. Gates with high drive are called buffers and can drive a larger number of loads than normal gates. But here the normal drive is enough for an LED.

The 7486, 7408 and 7432 are quad XOR, AND and OR gates, respectively. Below are detailed pinout diagrams for each:

See if you can relate the connection to this diagram of a full adder from the link you posted:

You'll see that it's using 2 XOR's (7486), 2 AND's (7408) and one OR (7432).

One final note: 74 series bipolar TTL logic (74xx, 74LSxx, 74Sxx, 74Fxx) defines an unconnected input as a logic '1'. This does not work for CMOS gate logic types (74Cxx, 74LVCxx), which require all inputs to be tied either to a driving signal, to 0 (GND) or to 1 (+5V / VCC.)

• Can you please provide links or citations for the graphics you copied into your answer? – Elliot Alderson Jul 12 at 22:35

You are simply confused at the difference between logical 1/0 and input/output characteristics of the logic family ICs you are using.

You may find that this document helps you. You can also download some of the very old Logic Databooks such as this TI version from the Internet Archive.

Both these documents allow you to see the implementation of the logic gates, and here is one view of a 74LS00 2 input Nand gate:

From the schematic you may notice:

1. There are two inputs (A and B) which if you pull them to ground your driver (manual switch or logic gate) will have to SINK current.
2. The output of the gate has a current limited high drive (Q4 and the 130 Ohm resistor) so you have to design your circuit recognizing this current limit.
3. The output of the gate also has a current limit when driving a low voltage out. The current is limited by the base drive for Q5 in the diagram above.

From the datasheet you can glean the following information:

For the 2 input Nand gate (74LS00) the input current is about 220uA when held low (0V) and approx 1uA when held high (5V).

For the output the maximum sink current for a low (close to 0V) is recommended as 8mA and for a high output the current limit is recommended at 400uA.

How can the output from a single logic gate/DIP switch supply input for multiple gates?

Like this:

simulate this circuit – Schematic created using CircuitLab

You separate you thinking into two branches:

1. There are logic signals based on 0 or 1. Don't consider the DC characteristics here, you simply consider the logic level. From any given output you can 'drive' a large number of inputs on other logic elements.

2. There are DC load rules for the logic elements, and you will see these specified in the datasheets in various ways. In many design resources they will discuss FANOUT and FANIN, but this really relates back to the current flow into and out of the logic elements.

You can now see that for example in diagram above one 74LS00 output 'drives 3 other inputs on three other 74LS00. Providing NAND1 can sink the current required from NAND2,3,4 all will be ok. In fact the normal design rule for most logic is to assume a fanout of no more than 10 ...ie one output can drive the logic level well within spec of 10 other inputs.
When designing logic using a toolset, you don't have to think about FANIN or FANOUT it's built into the tool and will warn you when you exceed the capability of the device.

So in summary, don't think about the voltage or current levels, think about logic levels. Many inputs may be connected to an output and while at a DC characteristic level these are all in parallel you normally don't have to consider this. In complex systems there are 'buses' that connect together 10's to 100's of inputs and outputs (many tri-state) where you only consider the logic levels during the early design. the DRC (Design Rule Check) for your toolset will warn if you break the rules.