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I'm devising a circuit to control the shutdown input on an integrated circuit. The IC accepts a high impedance input (can't be pulled to any voltage) to enable operation, or it can be pulled down to disable operation.

I'm trying to control it with a logic signal which is either 0V or 3.3V. This would be relatively simple with a low-side NPN/N-fet. However I want it to operate in an inverted way, where a 0V input will result in the output being pulled down and 3V3 input will give a high impedance output.

What kind of circuit could I use for this? I've thought about adding a transistor inverter before a low-side transistor, but if possible i'd like to reduce the part number.

Here's a diagram of how the circuit should operate:

circuit overview

Edit: datasheet of the IC

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2 Answers 2

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This question would be much easier to answer if you had provided a link to the datasheet so we could read the specification for ourselves. However ...

The IC accepts a high impedance input ...

This is most likely incorrect interpretation. The usual configuration is that the IC presents a high impedance to the circuit that is driving it. That means that it will require very little current to control the enable input.

... (can't be pulled to any voltage) to enable operation, ...

This should possibly read "can be left floating to enable operation". This suggests that the enable input has an internal pull-up resistor to force a logic high if it is left unconnected.

... or it can be pulled down to disable operation.

This bit is correct. A simple connection to ground using a transistor, GPIO, etc., will do the trick.

However I want it to operate in an inverted way, where a 0V input will result in the output being pulled down and 3V3 input will give a high impedance output.

0 V pulling the input down is not inverted - it is direct connection. If the chip accepts 3V3 logic then you just directly connect your signal to the enable input. If not then you may need a logic level converter.

  • 0 V in will disable the chip.
  • 3V3 in will drive the high impedance input of the chip high using the low impedance of your source signal.

In general, we use low impedance sources to drive high impedance loads. This way one output can drive multiple inputs.


From comments:

I'm talking about the 'SHDN/UVLO' pin. In normal operation, it's used for undervoltage detection and should not be influenced (hence I need to apply a high-impedance load). When shut down is desired, it should be pulled low.

enter image description here

It's clear from Figure 1 that SHDN/UVLO is an input so it is the load, not the voltage divider to the pin (which is the source). You just need to take into account that it is trying to take 2 μA from the divider.

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  • \$\begingroup\$ Here's the datasheet: analog.com/media/en/technical-documentation/data-sheets/… I'm talking about the 'SHDN/UVLO' pin. In normal operation, it's used for undervoltage detection and should not be influenced (hence I need to apply a high-impedance load). When shut down is desired, it should be pulled low. \$\endgroup\$
    – Niek
    Jul 13, 2019 at 11:05
  • \$\begingroup\$ See the update. \$\endgroup\$
    – Transistor
    Jul 13, 2019 at 12:21
  • \$\begingroup\$ The pin is connected to the external voltage divider R3/R4, which enables undervoltage detection during normal operation. What I'm trying to do is make a circuit which when presented with 0V 'overrides' the voltage divider and pulls the pin to ground. When the circuit is given 3V3, it should not interfere with the voltage divider (i.e. present a very high impedance). Does this clarify what I'm looking for? \$\endgroup\$
    – Niek
    Jul 13, 2019 at 17:19
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Through experimentation, I've found a configuration that works: a schottky diode.

The 'UVLO' pin will be around 1.5V by the voltage divider. When 3.3V is applied it will not be influenced, but when I pull the input down to 0V the output will be low enough to disable the IC.

enter image description here

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