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Take for example a ripple carry adder, how does a circuit handle delays of some elements?If ripple carry adder starts working from some clock cycle, we can't expect that it will have correct results on the next clock cycle.

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No.
The ripple effect takes as long as it takes. It is up to the designer to make sure that the result is stable when it is used.

On purpose I don't write "the next clock edge" as the designer can invoke a so called multi-cycle path. In that case the result is not used until two or three clock cycles later.

If this is supposed to be the next clock edge, the designer must make sure the clock frequency is low enough.


How are delays introduced?Are counters used for that purpose?

Sometimes but in general you try to avoid adding delays. From what I gather from your questions is that you are looking for the answer how to do what we call in the profession timing closure.

Timing closure is a very complex process which involves various solutions depending on if you have set-up, hold time or maximum frequency problems. It would take many pages and is thus beyond the scope of stack exchange to tell you even the beginning principles and techniques, but I hope with that as search term you learn a lot from the internet.

Just for completeness: delays are only added when a register has hold-time problems but has slack in its set-up time.

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  • \$\begingroup\$ How are delays introduced?Are counters used for that purpose? \$\endgroup\$ Jul 14, 2019 at 14:18
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The circuit doesn't, the designer has to do. Maximum delays are typically fixed, you have to plan the circuit appropriately, which potentially means that you design it to wait one clock cycle.

If needed, the designer can route out a "ready/conversion done etc" signal.

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  • \$\begingroup\$ How is the delay implemented?Do designers use counters or is there some another approach? \$\endgroup\$ Jul 14, 2019 at 12:39
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    \$\begingroup\$ @user3711671 You seem to have a fundamental misunderstanding of how combinational logic works. Delays are not introduced, they are inherent in the operation of the circuit. We don't design the delay values, we design in spite of the delay values. The designer must make sure that all combinational logic has settled before using (or latching) the output of that logic. \$\endgroup\$ Jul 14, 2019 at 14:28
  • \$\begingroup\$ @user3711671: if needed, you just intoduce a chain of inverters or schmitt triggers \$\endgroup\$
    – Sascha
    Jul 14, 2019 at 14:30
  • \$\begingroup\$ @ElliotAlderson I know that delays are an inherent problem but these delays have to be taken in mind, that's what I was interested in.How are circuits designed with delays taken into account?If we have to idle for certain amount of clock cycles, then how do we achieve this idle state?Maybe using counters? \$\endgroup\$ Jul 14, 2019 at 14:48
  • \$\begingroup\$ @user3711671: for most switching elements a counter is not efficient, since the clock cycle of your counter is going to be on the order of your switching times, whus you can delay the trigger (e.g. using the RC time constant of the input) \$\endgroup\$
    – Sascha
    Jul 14, 2019 at 15:46
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You imply in your question that delays are being "introduced" or "implemented". They are neither implemented nor introduced
Delays happen because gates take time to pass signals. They are intrinsic. If you have a long adder with a lot of gates, it will have a long delay, and you have two options:

1) Lower the clockspeed so that each cycle lasts longer than the delay.

2) Implement a multi-cycle adder where part of the addition happens on the first cycle, then part on the second, etc. Then set your clockspeed so that the slowest stage of your adder has less delay than the duration of your clock cycle. This can be done using common logic elements such as D flip flops that take a value on clock cycle transitions.

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Ensuring various types of delay are properly evaluated so a circuit operates properly is the responsibility of the designer of the circuit. The designer must ensure that the operational speed of the function can meet the overall requirements.

Take your ripple counter example - an asynchronous design. If I were to implement such a circuit using separate flip flops such as this one, I would need to know the worst case propagation delay which is 14 nsec.

In addition, if using D flip flops (where the D input is fed from the #Q output), the setup time would also need to be evaluated which in this case is 7 nsec.

So the maximum rate at which such a counter could be operated at for a single device is 47MHz for guaranteed operation (provided the maximum toggle rate of the device is rated for it, which in this case is true).

For more bits, all the delays need to be analysed if there must be a particular duration where the output result is correct.

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Delays, rise times and setup times are defined by design due to CMOS voltages, RdsOn, Ciss, Ciss etc and given in no times for each discrete part.

You can choose a multiphase clock to decide when the output is guaranteed to be settled to improve clock rates by a state diagram pipeline so you get what you compute for worst case delays to guarantee the logic is valid within these delays for the next clock edge and state values.

All FET including those used in CMOS have a 50% production tolerance for Vt = Vgs(th) and a temperature with Vdd (=Vgs) dependency for all these delay times.

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