The modular 5V-powered design's module is having two output clocks (21 MHz and 3.5 MHz) to other modules in the system. I am looking for the best way for buffering these signals so that they would be enough fanout / strength and least distortion for several distant wires attached within the system. Length can be considerable, up to 60 cm (25 inches).

The choices are: use LVC1GU04 unbuffered inverter (the same type used in the Pierce oscillation circuit), use buffer like LVC1G126, or LVC1G14 Schmitt trigger.

During investigation I found out several pieces of information making me a little stuck with making the conclusions.

  1. The functional difference between LVC1GU04 and LVC1G126. Comparing the datasheets I see no much difference. Historically, I would expect 1G126 to be more load-capable, but here it looks like just buffer with enable. Thus is there any rationale on using 1G126?

  2. This document called Use of the CMOS Unbuffered Inverter in Oscillator Circuits says:

An unbuffered inverter itself may not have enough drive for a high-capacitive load. As a result, the output voltage swing may not be rail to rail. This also will slow down the edge rate of the output signal. To solve these problems, a buffer or inverter with a Schmitt-trigger input can be used at the output of the oscillator.

But I do not see proof of this in the datasheets of 1GU04 and 1G126, both circuits are being tested by the 30 pF and 50 pF loads.

  1. The starting, general clock buffering circuit I obtained looks like the follwing:


simulate this circuit – Schematic created using CircuitLab

It uses standard DIP packaged 74LS04, series resistor to match impedance (and I guess limit output current), and pull up to ensure high level is maximally close to 5V as LS04 is TTL and is not rail-to-rail. Is there any better buffering circuit for the LVC1G(U)04 or other related small logic 1G chips in this family? What would be the frequency limit of the input clock?

I am looking for guidance. I can not change design and length of the traces in other modules, thus the effort is only about designing proper buffering/redriver circuit.

  • \$\begingroup\$ For that distance, I would be looking at something designed to be a backplane driver (Iol and Ioh of at least 20mA and preferably more). TI (and others) have such things. Take a look at: ti.com/logic-circuit/buffer-driver/non-inverting-buffer-driver/… \$\endgroup\$ – Peter Smith Jul 15 '19 at 8:25
  • \$\begingroup\$ Thank you for the link! According to the list, all three chips LVC1G04/LVC1G126/LVC1g14 with +-32mA would satisfy these requirements. \$\endgroup\$ – Anonymous Jul 15 '19 at 8:35
  • \$\begingroup\$ It's not clear what can and can't change in your design. For the 21MHz clock my first concern would be cabling to make sure you have a relatively controlled transmission line. Also keep in mind that you can connect gates in parallel to increase the driving strength. \$\endgroup\$ – joribama Jul 16 '19 at 3:00

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