In other words, if signal goes high and triggers the always block, will the block be synthesized in a way that the behavior in the if (signal)... block is reliably performed (since signal is now high)? Or will this behavior only be reliably performed after a clk rising edge when signal is already high?
always @ (posedge clk, posedge signal)
begin
if (signal)
begin
// do stuff
end
end
I've simulated similar code in Active-HDL, showing that // do stuff is performed after a signal rising edge.
My prior experience with HDL makes me uneasy about this code, but I'm new to Verilog and wanted to clear up any misconceptions.
Related questions:
- Is synthesis of code like this vendor-specific?
- Are VHDL sensitivity lists handled in a markedly different way?
I am trying to implement something like a SPI slave peripheral, so the two important inputs are the chip select and the clock. Since the clock will only ever be used a relatively long time before and after the chip select changes state, I'm using them both in the sensitivity list with the chip select being essentially an asynchronous set, as you suggest. Ordinarily I'd bring signals in synched with a shift reg to sequence behavior, but I don't have access to a particularly fast clock, so I'm trying to understand better to create a safe way to sequence things.
