I am building a pasive bandpass filter with the band pass between 134MHz and 139MHz. It is a third order eliptic filter, with theoretical attenuation of around 50 dB for the stop band and less than 1dB ripple in the pass band. This is the schematic:


And here is the response of the filter in a LTSpice simulation, from 50MHz to 500MHz:


Focusing on the pass band:

Pass band simulation

Everything seems to work fine enought for my requirements (I plan to use it to receive signals of small bandwidth from 137,1MHz to 137,9MHz, and S11 < -10dB there, so I should not have any problem. Besides, I thought about using a 20dB LNA to overcome the insertion loss of the filter).

After the simulations, I created the PCB in KiCAD. This is the final result:


It is just a microstrip (calculated with relative permitivity of 4,5 for FR4, with a thickness of the PCB of 1,6mm and 1oz of copper to have 50Ohm impedance) with the components attached to it. The board is 30mm x 21mm (I tried to keep it the shortest possible to avoid losses and parasitic effects). The PCB has only two layers and the bottom one is just a ground plane, connected both to the SMA connectora and to the upper groumd plane by the bias.

This is the filter bluid, where ±5% 0805 components are used:


I know that soldering can be improved, I am planning to buy better tools in the near future. However, all the connections are well soldered and the filter should work properly.

I then tested it with my homemade spectrum analyzer: a SDR with a BG7TBL noise source. The software used is callecalled Spektrum. It features a relative mode, where it records and averages the response of the noise source itself and then you can connect the filter to see its real response. This is the result, again, ploted from 50MHz to 500MHz:

real response

Here, I see some serious problems:

  1. The losses in the pass band are 28dB and not the simulated 5dB
  2. The attenuation is of only 8dB, and not the simulated 50dB
  3. As we increase in frequency, the effect of the filter dissappears

I have no clue about why this is happening. I have revised the schematics, simulated everything again, revised the PCB design, and even built 4 of these filter to ensure that it was not a soldering problem, but all of them have similar frequency responses. I have also tried different SDR software with no luck neither.

What am I doing wrong? How can I solve this problem? Any advice or improvement to the design will be appreciated.

Thank you very much in advantage.

Edit: In case the LTSpice/KiCAD files were needed, here is the github of the project:


  • \$\begingroup\$ Do you have a ground plane on the bottom layer? Do you have any conductors on any other layers besides top? If so then show them. \$\endgroup\$
    – Voltage Spike
    Commented Jul 15, 2019 at 17:32
  • \$\begingroup\$ What are the component sizes? 0603? \$\endgroup\$
    – Voltage Spike
    Commented Jul 15, 2019 at 17:34
  • \$\begingroup\$ @laptop2d It is a 2-layer PCB. The bottom later is a ground plane, connected by bias to the ground in the top layer \$\endgroup\$ Commented Jul 15, 2019 at 17:34
  • \$\begingroup\$ @laptop2d They are 0805 +-5% \$\endgroup\$ Commented Jul 15, 2019 at 17:35
  • 1
    \$\begingroup\$ @user3141592, 100 MHz is fast enough you need to worry about which inductors and capacitors you use. \$\endgroup\$
    – The Photon
    Commented Jul 15, 2019 at 18:53

2 Answers 2


If you built the above board with superconductors and used ideal components then the PCB would match up with the simulation nicely.

There is no parasitics being modeled in the simulation. The parasitic capacitance between planes will be approx 2pF between the connectors on the sides and the ground plane (I assumed 20mm by 3mm for the copper). The parasitic inductance of the same --roughly-- 20mm x 3mm conductors will be about 2nH.

The capacitors will have ESR and ESL that limit there effectiveness at high frequencies. Make sure you at minimum use low ESL capacitors. The ESR and ESL need to be modeled in spice, or use s-parameter models. Looking at the simulation the parasitics on the 620pF cap made the most difference. It may be better to select different component values with better parasitics. Either way, you need to start looking at frequency graphs of the components themselves.

enter image description here Source: https://ds.murata.co.jp/simsurfing/mlcc.html?lcid=en-us#

Another problem that may arise is some SMT inductors lose their effectiveness at high frequencies, I don't know if this is the case for the design above, but if so then the inductors would be non-existent after a given frequency and could be considered open circuits.

enter image description here Source: https://ds.yuden.co.jp/TYCOMPAS/ut/detail?pn=LBM2016T2R2J%20%20&u=M

Component tolerances also need to be accounted for. http://blog.optimumdesign.com/clearance-and-creepage-rules-for-pcb-assembly

  • \$\begingroup\$ Thank you very much! I now have the info I needed to continue learning about it. I will take care abour the datasheet of the components I buy the next time \$\endgroup\$ Commented Jul 15, 2019 at 20:09
  • \$\begingroup\$ I am reaching the conclusion that it is imposaible to design this bandpass filter with discrete components. \$\endgroup\$ Commented Jul 16, 2019 at 12:18
  • \$\begingroup\$ So I found the datasheet of my capacitors and this is the only reference to their behavior depending on the frequency: imgur.com/a/M3mSlHJ . For 130MHz, the resistance seems to be around 1Ohm for the 620pF caps and more than 5Ohms for the others. Then, as the parallel branches of the circuit have $Z_0=1.9$, the resistance of the 620pF caps it too big, isn't it? \$\endgroup\$ Commented Jul 16, 2019 at 12:24

Your shunt stages are running with a characteristic impedance of \$Z_0 = 1.9\Omega\$. This is outside of the practical impedance range for most inductors.

Carefully model your inductors for losses and self-resonance, and try the model again.

  • 1
    \$\begingroup\$ You can't get 50 ohm resonators in a 50 ohm circuit using that design methodology. You need to look for better filter topologies. LTSpice doesn't take inductor parasitics into account because SPICE models ideal circuits -- it's up to you to know when you need to model parasitics, and how to do that. \$\endgroup\$
    – TimWescott
    Commented Jul 15, 2019 at 18:04
  • 1
    \$\begingroup\$ Thank you for the info. What terms can I search online to learn more about it and properly design the circuit? And, by the way, how did you calculate those 1,9Ohm? \$\endgroup\$ Commented Jul 15, 2019 at 18:08
  • 2
    \$\begingroup\$ @user3141592 that 1.9 Ohm is squareroot(L/C) where L and C are taken from a resonant circuit which is assumed to operate near its resonant frequency. L and C have that big reactances. You should have inductors with far smaller series resistance (with skin effect included) and the self capacitance of the inductor should be much smaller than C. BTW. The inductors should be tuned. It's quite a task in a circuit this complex. You should simulate what expectable capacitance and inductance errors cause \$\endgroup\$
    – user136077
    Commented Jul 15, 2019 at 18:54
  • 2
    \$\begingroup\$ It might get closed as too broad, but you might ask what filter topologies are used to implement what you want in the space you have. My hands-on knowledge stops at about 28MHz and 1990, but back when I paid close attention, you would implement this sort of bandwidth at this sort of center frequency using a helical filter. Do a search, but Toko used to have a wide range of them. \$\endgroup\$
    – TimWescott
    Commented Jul 15, 2019 at 19:04
  • 1
    \$\begingroup\$ Note that another problem you have is that you want a bandcenter/bandwidth ratio of around 26-27, which is getting pretty ambitious from a loss standpoint for discrete components, and nearly impossible from a precision standpoint (just do your ideal simulation with a monte carlo simulation using \$\pm\$10% component tolerances). \$\endgroup\$
    – TimWescott
    Commented Jul 15, 2019 at 19:04

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