For sure not the first time for me visiting this awesome site, it saved me quite a few times - this time, however, I have a specific question ... would be great if someone could help me with this!

I need a software-tunable oscillator with frequencies from 100 kHz to 2 MHz and an amplitude of at least 10 V(pp). So the -3dB bandwidth should be high enough to have a stable gain between 100k-2MHz. I realized that this is already quite a challenge. Well, I decided to go for the famous AD9850 which I successfully hooked up on an Arduino and it runs like a charm! However, the amplitude of the signal is only 1 Vpp, so I do need an amplifier. This is where it's hard for me to wrap my head around.

So far, I used OpAmps a lot. Here, this doesn't appear to be the best approach since a gain of at least 10 with 2 MHz bandwidth and 10 V(pp) sounds like I need an expensive OpAmp with both high GBP and insane slew rate ... So I decided to go for an common emitter amplifier! I read quite a few articles, but as a hobbyist - hell that's confusing stuff! However, I got a circuit running and the simulation looked quite promising as you can see below - and I am sure, those are not necessarily the best values to choose. I used a BC547C I found around and built the circuit ... and was quite disappointed when I hooked up the AnalogDiscovery2's network-analyser.

enter image description here

Unfortunately, I don't have an image of the Bode-plot anymore. Aafter digging deeper in the internet I figured that the collector-base parasitic capacitance, about 9 pF for the BC547C, is killing me - when inserting this capacitance (C3 in the image below) I get the EXACT same curve as measured with the AnalogDiscovery2 in the real circuit.

enter image description here

Well, crap! There is no way to get around this capacitance here ... again I went for a search on the internet and found some "HF"-labelled transistors with high GBP and (promised) low capacitance-values for C(cb). Now, here are some more details about the circuit's intended use:

  • Impedance of the (filtered) AD9850's output is 200 Ohms (at least that's what I designed the filter for and that works quite well...)
  • Output is going to be hooked to an high impedance conductivity sensing circuit with at least 200 kOhm input impedance (which is R6 here, 1 MOhm is just an educated guess, could even be more...)
  • ... so effectively I need an VOLTAGE amplifier, not so much of an power amplifier.
  • I have a voltage source for up to 35 V as supply - this should not be a problem (above this is V2 with 20V here)
  • I do have some "HF" transistors/JFETs here, including the SC1730, BF545A, BF959, BFS17 an NTE312 and a BFW92 that do all have significantly lower C(cb) values

I would really appreciate some advice on:

  • if the use of one of these transistors/JFETs or - more generally - any transistor/JFET with lower C(cb) and GBP can fix my problem, or if I am running in a totally wrong direction here
  • Would you recommend more than one gain stage for a stable 20dB gain between 100 kHz and 2 MHz?
  • and would it even be possible to go beyond +20dB?

Just one last thing: I would like to keep the cost of the circuit as low as possible, which is why I reckon a CE-amplifier (or something like this) would be a good solution since transistors/JFETs are cheap.


Thanks for all your answers, great to get such nice help! Here a few things I'd like to share:

I looked it up, for sure C(cb) was included in the BC547's LTspice model - stupid me. Although I did made some substantial progress in understanding impedance, clearly I am bad in spotting it in action. The AD2's input impedance with its 25 pF as pointed out by some of you seems to be a major problem.

I rebuild the model posted by Bruce below with parts I had laying around, I've got a picture of the LTspice circuit:

enter image description here

And the actual thing:

enter image description here

I follwed the general advice and soldered it to a perfboard to minimise parasitic capacitance - and well, it works great! (although looking a bit like a bungling...). Below I got the actual Bode plot from the simulation and of the measurement with my AD2:

enter image description here

Since it's hard to see: I've got 25.3 dB @ 100 kHz, 25.7 dB @ 1 MHz and 25.3 dB @ 2 MHz - awesome!

The only thing that I noticed is a distortion of the wave form when using 20 V as supply voltage, that also occurs in the LTspice simulation, even worse there.

enter image description here

Now that seems to come from the high gain trying to amplify the signal beyond the actual supply-voltage. I turned up the voltage to 25 V which almost eliminated the distortion - 30 V were even better! However, that's where R2 whith it's 1/4 W power rating seems to say good by since it heats up quite quickly. I calculated the mean power dissipation with spice and yupp, 350 mW it is. So I guess I will switch to a 1 W resistor on my final amplifier pcb to be on the save side.

  • \$\begingroup\$ You will probably want to look at cascoding, two-quadrant operation, current mirrors, and current sources/sinks. And perhaps methods needed in discrete designs to deal with variations in BJT devices. In effect, you are building a discrete amplifier. What worries me more is that you appear to want something that doesn't even show some "roll-off" near your peak desired frequency of 2 MHz. So this makes me wonder how FLAT you expect the gain to be over the range you specified. When you say "at least 10V," how much variation are you allowing, exactly? Or is roll-off okay, so long as 10V is met? \$\endgroup\$ – jonk Jul 15 '19 at 23:14
  • \$\begingroup\$ And do NOT even think about a solderless protoboard. The parasitics on a protoboard are like 5 pF between adjacent rows. That will murder anything you attempt. If you prototype this by hand, use dead-bug construction and keep as many of the important connections as tight and short as possible. \$\endgroup\$ – jonk Jul 15 '19 at 23:17
  • \$\begingroup\$ LTSpice should already be simulating the base to collector capacitance. Show us your layout, please. \$\endgroup\$ – TimWescott Jul 15 '19 at 23:21
  • \$\begingroup\$ How much distortion can you accept on the output? \$\endgroup\$ – Bruce Abbott Jul 16 '19 at 0:07
  • \$\begingroup\$ R6 is actually "Input impedance: 1MΩ||24pF" if you used a BNC patch cable you would add even more load capacitance \$\endgroup\$ – sstobbe Jul 16 '19 at 1:28

after digging deeper in the internet I figured that the collector-base parasitic capacitance, which is about 9 pF for the BC547C, is what kills me - when inserting this capacitance (C3 in the image below) I get the EXACT same curve as measured with the AnalogDiscovery2 in the real circuit.

Collector-Base capacitance should be included in the transistor model, so you don't need to add it. However you do need to add any significant external parasitic capacitances. A solderless breadboard typically has 2~3pF between adjacent tracks. Input capacitance of the AnalogDiscovery2 is 24pF. The -3dB cutoff frequency for 4.7kΩ and 24pF is 1.4MHz.

To reduce the effect of parasitic capacitances you can increase the transistor's Collector current and reduce the load resistance. You can also reduce DC gain to improve bias stability, and bypass the emitter resistor with a lower value to get the required AC gain and amplitude.

I took your circuit and reduced R2 from 4.7kΩ to 1kΩ, adjusted the Emitter and Base bias resistors to get about 12V at the Collector and 2V at the Emitter, and bypassed the Emitter resistor with 68Ω to get the required AC gain. I added 2pF between the Collector and Base to simulate external wiring capacitance, and another 30pF at the output to simulate the measuring instrument or load and wiring to it.

With this configuration the -3dB bandwidth was 23kHz to 3.5MHz, and the output amplitude at 2MHz was 13.7Vpp.

If you need even less amplitude variation over the pass band you can put a 'peaking' coil in series with the Collector resistor. I tried 20uH, which raised the 2MHz point to 0dB and extended the -3dB point to 6MHz.

Note that using a peaking coil may make the response more sensitive to load capacitance, as the coil and capacitor form a tuned circuit. With no load capacitance the simulated circuit exhibited a +3.5dB peak at 8MHz.

enter image description here

enter image description here

  • \$\begingroup\$ thanks a lot for this helpfull reply! I did try it out and it works like a charm! I added my findings to the EDIT part above in my main post - maybe someone has some more recommendations. I did play around a little with the values, especially of the load capacitance C3 to get a feeling for the dependency you mentioned - I guess I can just add a capacitor like C3 later if the peaking you described gets substantial due to a (potentially) much lower load capacitance? \$\endgroup\$ – mestoben Jul 16 '19 at 14:51
  • \$\begingroup\$ If the load capacitance is much lower then you won't need (or want) the peaking coil. If a range of load capacitance has to accepted it would be better to add an Emitter follower stage, which isolates the Collector from the output and reduces output impedance to drive higher capacitance loads. This only requires one extra transistor and one resistor (from Emitter to Ground). \$\endgroup\$ – Bruce Abbott Jul 16 '19 at 19:13

I think this is a good example of an XY problem. Instead of focusing on minimizing the input capacitance in the specific configuration you have chosen, try to modify the circuit in a way that removes the need to minimize the capacitance.

When you were learning about op-amps, you probably encountered the fact that the open loop gain of the amplifier does not matter as long as it is large. The closed loop gain of the amplifier is

$$H = \frac{A}{1 + AB} \approx \frac{1}{B},$$

where \$A\$ is the open loop gain and \$B\$ is the feedback fraction.

The same principle can be applied for the common emitter amplifier. Applying negative feedback will greatly reduce the variation of the gain.

However the variation of the open loop gain must be taken into account, since it is not large enough. You must increase the open loop gain until the response is within your specification. For example, let the open loop gain be in the range \$A\in[90, 110]\$. If you use \$B = 0.09\$, the closed loop gain will be \$10\$ at \$A = 100\$. The gain over the whole range is


As you can see the variation is greatly reduced. A 10% variation in the open loop gain has become a 0.1% variation in the closed loop gain. You can keep increasing the gain until you satisfy your specification, but be careful about stability issues.

To achieve the required open loop gain, you may need to cascade more than one amplifier. Have a look at the common emitter common base cascode. It has the benefit of mitigating the Miller effect.

  • \$\begingroup\$ thanks, that actually looks interesting. I did some searching for CE-CB cascoding which kind of seems to be well suited for this problem. However, now there are effecively two circuits to calculate - aweee, that's going to take a while for me to get through it ;) I'll try it next week hopefully \$\endgroup\$ – mestoben Jul 16 '19 at 14:54

A single-transistor CE amplifier with 10pF Cob and gain of 10x will have 110pF input capacitor, ignoring the emitter-base capacitance.

With an Rsource of 200 ohms, the 110pF Cin yields 22 nanosecond time constant, or 45MegaRadians 3db. In Hertz, that is 45/6.28 or ~7MHz. Thus about 1 dB droop in the frequency response at 2MHz, due to CMillerInput and the Rsource.

Have you planned for that? Does input response drop of 1dB bother you?

  • \$\begingroup\$ ok, although you lost me a little with your calculation I think I get the effect this has on my planings ... I reckon 1 dB would be ok, although I would hope for it to not be much more in total. Thanks for this hint! \$\endgroup\$ – mestoben Jul 16 '19 at 14:58

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