I don't under this layout figure (5.c) in pic attached. This is a screenshot from research paper in this link:-


Alternate link for the paper in case if you are not a member of IEEE https://1drv.ms/b/s!AuHq5DWFZ2WugWlDfRyx1OofH1-N

enter image description here

My basic Curiosity is that layout are generally in shape of squares and rectangles, but in this layout what is that blot (ink drop) like thing in fig 5.c

  • \$\begingroup\$ As the article is about power, my guess is that it is some "power in this area" graph. Second guess: purple and yellow are separately powered blocks. \$\endgroup\$ – Oldfart Jul 16 '19 at 5:12
  • \$\begingroup\$ @Oldfart Sir, I am doing a project in this paper.can you tell me how can I achieve this layout like which software i need to use to obtain this type of layout. \$\endgroup\$ – Rohit Jul 16 '19 at 5:19
  • \$\begingroup\$ Sorry, can't help you. Layout and the related tools where driven by other experts in the companies I worked for. I would also suggest you change your question more along the lines of: "what tool produces this type of layout?". \$\endgroup\$ – Oldfart Jul 16 '19 at 5:44
  • \$\begingroup\$ @Oldfart Thanks for suggestion \$\endgroup\$ – Rohit Jul 16 '19 at 5:57
  • \$\begingroup\$ I am not registered at IEEE.... perhaps if you have access to a link for the original publication outside IEEE would help. \$\endgroup\$ – Brethlosze Jul 16 '19 at 6:05

The "blob" in the picture is a depiction of an ASIC physical layout created by a place-and-route algorithm. These algorithms often use randomized simulating annealing methods to place logic within a grid. These methods don't inherently favor a rectilinear layout; they often create layouts with an organic, cloud-like appearance. Similar algorithms are used for FPGA design as well.

These sorts of layouts are not uncommon in larger modern digital designs, like microcontrollers or SoCs. A few examples can be seen in die shots, including:

  • This ATTiny4 on Zeptobars. Manually laid-out blocks can be seen in the top left and bottom, probably for analog functionality and flash memory.

  • This PIC24, also on Zeptobars. Similarly, there are a couple more regular regions which probably contain flash memory, SRAM, and/or analog components.

  • The Apple A12 Bionic SoC on Anandtech. Interestingly, this layout is composed of many different regions of automated layout, with regular rectangular blocks of what is probably SRAM positioned throughout the die.


This looks like a power integrity tool in a VLSI back-end flow, likely Cadence Voltus or similar.


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