Your observations are all correct on the measurement differences between the 74LS TTL series “Gate” and “Buffer”, including the discrepancy in one line of the Wiki page which led to your good question. It should have said digital buffers can drive more **current than their “standard” equivalents.
In TTL this is done by design using resistor values to define this. In CMOS, it is done by design for transconductance gain, \$g_m\$ whose inverse becomes RdsOn. This is graphed in some Application books by a typical Ron vs Vdd curve or in datasheet as guaranteed values for nom. & worst case (min or max) \$V_{ol} @ I_{ol} , V_{oh} @ I_{oh}\$ where Ron is the incremental ratio of V/I, e.g. (Vdd-Voh)/Ioh with nom. at room temp and Vdd and worst case over operating temp often rated at Vdd-10% such as 4.5V.
At the time of this answer the Wiki page for Digital Logic also made a similar error that you discovered.
It is also called a unity gain buffer because it provides a gain of 1, which means it provides at most the same voltage as the input voltage, serving no amplification function.
The wise reader will observe the contradicting use of “gain” in this Wiki page.
Since logic is actually a non-linear ANALOG circuit, there is voltage and current gain in the grey zone between logic levels (>10 for both V & I) , yet there is both NO incremental voltage gain at the valid logic levels. While TTL has a standard current gain or “fanout” of 10 , “buffers” have more current drive depending on which buffer IC you can choose . ( 4mA, 16, 32 or even 50mA for some)
“Unity gain” is a misnomer and simply means the logic levels are identical for both input and output when loaded to the “safe immunity” thresholds.
The actual threshold for ALL TTL families including 74HCT’ CMOS (TTL compatible) inputs is 1.3V+/- 0.1V typ for two Vbe diode drops. When you examine each family from 74xx to 74Lxx to 74LSxx to 74Fxx to 74Sxx you will see how each “input design” is different, yet has the same equivalent circuit of 2 diode drops with bias currents that require more for a “0” than a “1” because the saturated NPN common emitter drivers perform at max speed with more current for a “0” and for the “1” they use NPN emitter followers with some 2V drop from Vcc below which they drive more current but above, which they are fixed.
- In some cases, where noise is really bad and the design margin may improve, by adding some R pull-up which gives a full output voltage swing to Vcc, for long wired signals, but is rarely needed. When crosstalk is excessive, the designer must avoid tightly bundled signal wires or long close parallel traces due to coupling capacitance of ~1pF/cm.
Therefore it correct to say it has current gain but the incremental gain from input voltage levels drops to zero at the valid binary logic voltage levels, but then the absolute current gain is fixed meaning Ioh/Ilh and Iol/Iil.
The speed is determined by the rated capacitance load (e.g. 15 pF)and the drive currents with standard or Schottky type BJT’s together with the resistance controlled drive current and its associated power rating.
