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The TI 74LS00 is "quadruple 2-input positive-NAND gates" and the 74LS37 is "quadruple 2-input positive-NAND buffers."

The pinouts are identical. The LCCC package is documented exactly the same for both and, though the DIP package pinouts are labeled slightly differently (pins 9/10 are labeled "3B/3A" on the 74LS00 and "3A/3B" on the 74LS37), this this should make no difference in actual operation since there's no difference between the two inputs of a NAND gate.

The switching speeds may be slightly slower for the 74LS37; 12/24 ns typ/max versus 9 or 10/15 ns typ/max for the 74LS00, but I don't know if this might be simply because I'm looking at (the data sheet for) an older part for the 74LS37.

The input current draw seems the same for both.

The major difference appears to be the current capacity of the outputs; the 74LS00 sources up to 0.4 mA when high and sinks up to 8 mA when low; the 74LS37 sources up to 1.2 mA when high (3x) and sinks up to 48 mA (6x) when low.

Is this output current capacity the difference between this 74LS00 "gate" and 74LS37 "buffer"? According to the Wikipedia description of a "digital buffer" a buffer would offer better input characteristics, which don't seem to be different here. (Almost all of the other parts labeled "buffer" have open-collector or tri-state inputs.)

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Yes, the ‘LS37 is a buffer. The high drive figure is used for driving higher fan-out loads. Some other logic gates have equivalent high-drive ‘buffer’ versions. There are also some that are open-collector so that they can be used for wired-or buses and logic. There are still others designed to drive transmission lines.

At any rate, higher current is sometimes needed for large TTL fanout because each driven input presents a DC load that sources some current when the driven signal is low. High drive buffers increase the number of loads that can be reliably driven low.

Buffered outputs are also needed when termination is used to improve signal integrity - especially sensitive signals like clocks.

CMOS and LVCMOS gates also come in ‘buffer’ versions. The game is a bit different. Although CMOS inputs present no DC load, high drive helps CMOS overcome delay due to capacitive loading: it improves switching time. However, like TTL, the high-drive CMOS types help when termination is used.

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  • \$\begingroup\$ Oh, I see. I'd missed this line in the Wikipedia's list of 74xx parts: "Output column - a blank cell means [an output] with the ability to drive ten standard inputs of the same logic subfamily (fan-out NO=10). Outputs with higher output currents are often called drivers or buffers." \$\endgroup\$
    – cjs
    Jul 16 '19 at 6:46
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    \$\begingroup\$ One weird trick you can do with gates: tie them in parallel to increase the drive. \$\endgroup\$ Jul 16 '19 at 6:53
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Your observations are all correct on the measurement differences between the 74LS TTL series “Gate” and “Buffer”, including the discrepancy in one line of the Wiki page which led to your good question. It should have said digital buffers can drive more **current than their “standard” equivalents.

In TTL this is done by design using resistor values to define this. In CMOS, it is done by design for transconductance gain, \$g_m\$ whose inverse becomes RdsOn. This is graphed in some Application books by a typical Ron vs Vdd curve or in datasheet as guaranteed values for nom. & worst case (min or max) \$V_{ol} @ I_{ol} , V_{oh} @ I_{oh}\$ where Ron is the incremental ratio of V/I, e.g. (Vdd-Voh)/Ioh with nom. at room temp and Vdd and worst case over operating temp often rated at Vdd-10% such as 4.5V.

At the time of this answer the Wiki page for Digital Logic also made a similar error that you discovered.

It is also called a unity gain buffer because it provides a gain of 1, which means it provides at most the same voltage as the input voltage, serving no amplification function.

The wise reader will observe the contradicting use of “gain” in this Wiki page.

Since logic is actually a non-linear ANALOG circuit, there is voltage and current gain in the grey zone between logic levels (>10 for both V & I) , yet there is both NO incremental voltage gain at the valid logic levels. While TTL has a standard current gain or “fanout” of 10 , “buffers” have more current drive depending on which buffer IC you can choose . ( 4mA, 16, 32 or even 50mA for some)

“Unity gain” is a misnomer and simply means the logic levels are identical for both input and output when loaded to the “safe immunity” thresholds.

The actual threshold for ALL TTL families including 74HCT’ CMOS (TTL compatible) inputs is 1.3V+/- 0.1V typ for two Vbe diode drops. When you examine each family from 74xx to 74Lxx to 74LSxx to 74Fxx to 74Sxx you will see how each “input design” is different, yet has the same equivalent circuit of 2 diode drops with bias currents that require more for a “0” than a “1” because the saturated NPN common emitter drivers perform at max speed with more current for a “0” and for the “1” they use NPN emitter followers with some 2V drop from Vcc below which they drive more current but above, which they are fixed.

  • In some cases, where noise is really bad and the design margin may improve, by adding some R pull-up which gives a full output voltage swing to Vcc, for long wired signals, but is rarely needed. When crosstalk is excessive, the designer must avoid tightly bundled signal wires or long close parallel traces due to coupling capacitance of ~1pF/cm.

Therefore it correct to say it has current gain but the incremental gain from input voltage levels drops to zero at the valid binary logic voltage levels, but then the absolute current gain is fixed meaning Ioh/Ilh and Iol/Iil.

The speed is determined by the rated capacitance load (e.g. 15 pF)and the drive currents with standard or Schottky type BJT’s together with the resistance controlled drive current and its associated power rating.

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