Correct wiring of Cortex-M 10-pin Debug Connector

Question

The ARM Cortex-M 10-pin debug connector has five interesting signals, in the original PDF they're named:

• SWDIO / TMS
• SWDCLK / TCK
• SWO / TDO
• NC / TDI
• nRESET

For MCUs which only support SWD and which might even not have SWO (such as the STM32F030), I'm assuming the wiring is as follows:

• SWDIO / TMS: PA13 ("SWDIO")
• SWDCLK / TCK: PA14 ("SWCLK")
• SWO / TDO: Open
• NC / TDI: Open
• nRESET: NRST (Chip reset)

Is the assumption that nRESET means chip reset correct?

Because if it is, how about a larger device like an STM32F103:

• SWDIO / TMS: PA13 ("JTMS/SWDIO")
• SWDCLK / TCK: PA14 ("JTCK/SWCLK")
• SWO / TDO: PB3 ("JTDO/TRACESWO")
• NC / TDI: PA15 ("JTDI")
• nRESET: NRST (Chip reset) or PB4 (JNTRST)

Here, it's not clear where to connect nRESET anymore: To the chip reset signal (NRST) or the JTAG reset signal (JNTRST)?

Additionally, is it good practice to hook up both SWD and JTAG connection to a device that supports both (like the STM32F103)? If such a device should be only connected to SWD, does the meaning of nRESET change (i.e., when using JTAG maybe it's connected to JNTRST, but when only using SWD it's connected to NRST)?

Answer 1

nRESET and JNTRST do not fulfill the same purpose.

nRESET is full chip reset.
JNTRST is jtag reset, which is used for boundary scan.

The small 10 pin ARM SWD connector does not connect to JNTRST, that's a JTAG feature. You need the 20 pin version for that.

As also described in the manual of the ST Link V2, which has the 20 pin connector.
Note that NRST is always NRST.

nRESET is also optional. Only if you intend to disable access to SWDIO and SWCLK a full chip reset by the programmer is required.

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I often add a non-populated resistor in series with NRST to the programming connector to reduce risk of problems in the field. I can add this for prototypes, where it might be required. Production programming is not impeded by this.