I have a data signal, select and clock signal which I am sending from the FPGA to another chip and I need to constrain them so I don't violate setup/hold time etc.

I have tried to write and SDC file, but looking at the signal on the oscilloscope it doesn't seem to work, both clk and data transition happen at the same time. Setup is min. 1 ns and hold time is 0.2 ns. I have assumed 0.5 ns clock jitter and 1 ns pcb travel time. The tx_clk is derived from a PLL (2MHz). My sdc file looks like this:

create_clock -name clk_main -period 25.000 [get_ports {clk_main}]
derive_pll_clocks -create_base_clocks

set_output_delay -clock { u_nios_system|altpll_0|sd1|pll7|clk[1] } -max 2.5 [get_ports {tx_data[*] tx_sel}]
set_output_delay -clock { u_nios_system|altpll_0|sd1|pll7|clk[1] } -min -add_delay 0.3 [get_ports {tx_data[*] tx_sel}]

Am I misunderstanding how to calculate the appropriate delays or is there something wrong with the way i am applying the constraints?

Any help would be greatly appreciated.


1 Answer 1


In your set_output_delay -min statement, just enter the hold time as a negative value, like this:

set_output_delay -clock <clock> -min -<hold time> <port>

Have a look here: http://billauer.co.il/blog/2017/04/io-timing-constraints-meaning/

Here too: https://forums.xilinx.com/t5/Timing-Analysis/How-to-set-input-delay-and-output-delay-when-source-Synchronous/td-p/549028


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