# Testing spice model for common mode rejection ratio?

I've been trying to create a circuit to simulate common mode rejection ratio of an op amp to test the spice model's accuracy. While I've seen online that being able to use exact resistors only a simulator could use can be very helpful in determining CMRR, I can't seem to get a circuit to work. Anything I try either doesn't converge in simulation or doesn't give an accurate results. Any help would be appreciated.

EDIT: simulate this circuit – Schematic created using CircuitLab

I included a circuit schematic of my most recent iteration. I figured that I would extract the AC RMS voltage from the input vs output and calculate the common mode gain from the circuit. I first had the R2 resistor grounded but thought after that it should be ground w.r.t the AC common mode signal, so I attached it to my common mode signal generator.

I think it might be worth mentioning that at first I tried to connect a sine wave into the input rails via two 1k resistors and measured the open loop gain but it didn't converge.

• Are you trying to run a sweep and seeing how CMRR behaves? You can calculate CMRR by hand if you wanted to.
– user103380
Jul 16, 2019 at 18:56
• Yes, I would ideally like to run a frequency sweep and determine CMRR that way. Jul 16, 2019 at 18:57
• You'll have to create an expression on your own, i.e. creating a formula for CMRR while you're doing a frequency sweep. I don't know any tools for SPICE that will automatically give you the CMRR.
– user103380
Jul 16, 2019 at 19:02
• I see, if I figure it out i'll check back with a response. Thanks for the help regardless. Jul 16, 2019 at 19:04
• I have a concern that the relatively low value (1K) of the resistors is combining with the output impedance of the op amp to unbalance the ratios of R4/R1 and R3/R2. Any unbalance will reduce the CMR of the circuit. Could you try your simulation with larger values? 100K? Edit: Using LTspice and an OP-07 op amp, I get -20 dB improvement in CMR at 100Hz going from 1K to 10K. Perhaps you can give it a try. Jul 17, 2019 at 1:02

Use this circuit (and equation) instead:

It should be easy to come up with resistors in spice that are matched (in real life not so much and so you should use the other circuit in the application note).

This has worked for me, if it doesn't work the model may not be that realistic.

Another note: While the diagram shown in the OP has no ground on the 18V supplies, I hope that there was a ground between the supplies in the spice netlist. Otherwise spice would have a very difficult time finding the DC operating point and simulating, as al the voltages of that portion of the circuit would be floating, and the simulation wouldn't function very well. Supplies need to be referenced from ground, which I hope was done.

• I've actually looked at that one previously but was getting a saturated Vout when simulating it. Also yes my input rails were grounded haha I drew up that schematic for this question a little too quickly. I do have a question if you're knowledgeable on this particular circuit. What does it mean by delta Vout and delta Vin? Does it refer to the AC-coupled amplitude of the waves? Jul 16, 2019 at 19:52
• What range did you use for Vin, did you set the gain properly? Jul 16, 2019 at 19:54
• I used a gain of 3 with R2 = 2k and R1 = 1k, Vin was a 1V amplitude sine wave with 0V offset, rails were +/-18V Jul 16, 2019 at 20:04
• I might say the model is broken, on the amp's I have done this for, it works fine and I get numbers that are within a few percent, even on an AC sweep when compared to the CMRR graph in the datasheet. You might try a lower Vin than 1V and see if that helps. Jul 16, 2019 at 20:24
• I'll select this as answered since you've confirmed it worked for you. I'm going to revisit this circuit and play around with various op-amps and biases until I can get some results. Thank you for the help. Jul 16, 2019 at 20:31