i'm measuring 30 different voltages without common ground. Each voltage is measured by an AD7401A Sigma-Delta modulator/ADC. The signals go into an FPGA (Xilinx Spartan 6). But the I/O-Pins are limited. So I thought to switch between 2 ADC readings and this 15 times simultaneously. Instead of 30 I/O-Pins I need only 15 + 1 control line for the Muxes (TS3A5018DR). But of course the voltage readings need double the time. First 15 simultaneously readings, then switch to the other 15 and then demodulate their outputs.

Do you think that's implementable? And if so, without much effort in comparison to 30 parallel ADCs? Thanks for your help :)


Xilinx has a useful IOB input structure called IDDR / ISERDES. You can use this internally to demultiplex the signal.

Rather than switch every n samples, you could multiplex the data 2:1 at sample rate, and use both-edge or 2x rate input clocking to capture the multiplexed signals. Then your data would be at full rate for all 30 channels with no introduced skew between them.

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    \$\begingroup\$ +1 also: ISERDESes can be inferred, but the behavioral model is slightly different for ISE and Vivado, so it's generally not useful. \$\endgroup\$ – DonFusili Jul 17 at 6:44

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