0
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Why are LEDs on after executing this? LEDs on pattern is 1010:

module test(input clk,
input reset,
output reg[3:0] ledss

);

wire[4:0] dataread;
assign dataread=4'bzzzz;
always @(posedge clk)
begin

    if(dataread)
    begin

            ledss<=4'b1010;

    end


 end

endmodule
\$\endgroup\$
  • \$\begingroup\$ dataread is 5-bit wide, but you assign only 4 bits of it. \$\endgroup\$ – Eugene Sh. Jul 17 at 20:34
  • \$\begingroup\$ You mean you actually built this and saw the LEDs come on? How was it physically implemented? Is your hardware capable of implementing tristate logic on the dataread lines? \$\endgroup\$ – The Photon Jul 17 at 20:37
  • \$\begingroup\$ @EugeneSh. No metter same result if i assign 5'bzzzzz; \$\endgroup\$ – misha Jul 17 at 20:47
  • \$\begingroup\$ @ThePhoton Yes leds on .dont know why. i have altera IV EP4CE6 board. On silmulator ,everything works great and correct,but on really hardware leds is on in pattern 1010 \$\endgroup\$ – misha Jul 17 at 20:47
0
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When you set a signal in Verilog to z, you're allowing some external device to drive it high or low. In the physical implementation, if there isn't any actual device driving the net, then you're allowing random static electricity to drive it to either 0 or 1. You shouldn't expect to see an actual "Z" state in the physical circuit.

On top of which, in comments, you said this was implemented on an Altera FPGA. Recent FPGAs (since 1995 or so) generally don't implement actual tri-state logic on internal nets. If you design a multiply connected bus with tristate in your Verilog, the physical implementation will use multiplexers to approximate the effect of the tristate logic. But there will never be an actual moment when the net is un-driven in the actual FPGA.

Since you didn't specify whether you wanted a 0 or a 1 driven on those nets when your main driver applied "z", the synthesis tool was free to drive them to either 0 or 1 and had no way of knowing which you wanted.

\$\endgroup\$
  • \$\begingroup\$ Another question. I want to use dataread wire as 1 port ram ip output. How i detect when readed data isnot z? code what i want to work pastebin.com/8snsegVx if and case statement always executing,even when fill ram with zeros or ones \$\endgroup\$ – misha Jul 17 at 21:08
  • \$\begingroup\$ In hardware, dataread will never be z. You should read about the memory behavior in the Altera documentation. But there isn't even a read_enable input to the memory, so it will likely just output the value from whatever address it is given, even if you're also doing a write at the same time. You need to keep track in your own logic when the address given is something you want to read, and only act on the output of the memory when it makes sense to do so. \$\endgroup\$ – The Photon Jul 17 at 21:14
  • \$\begingroup\$ Something unexpected happend ,i think it is hardware issue or quartus bug. Case statement is always true,any time,no metter what is expression. for example in this code leds on pattern is 0110 pastebin.com/gt1Wqaj5 Memory initialization file not contains 32'b11111111111111111111111111111111 but case statement still return true. but if i assign dataread without case statement,it works good and leds on pattern is as expected pastebin.com/5mC7eC0S I going to throw this board into the trash and buy some xilinix XC6SLX9 board \$\endgroup\$ – misha Jul 18 at 3:33

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