# Verilog 'if' statement error

Why are LEDs on after executing this? LEDs on pattern is 1010:

module test(input clk,
input reset,
output reg[3:0] ledss

);

always @(posedge clk)
begin

begin

ledss<=4'b1010;

end

end

endmodule

• dataread is 5-bit wide, but you assign only 4 bits of it. – Eugene Sh. Jul 17 '19 at 20:34
• You mean you actually built this and saw the LEDs come on? How was it physically implemented? Is your hardware capable of implementing tristate logic on the dataread lines? – The Photon Jul 17 '19 at 20:37
• @EugeneSh. No metter same result if i assign 5'bzzzzz; – misha Jul 17 '19 at 20:47
• @ThePhoton Yes leds on .dont know why. i have altera IV EP4CE6 board. On silmulator ,everything works great and correct,but on really hardware leds is on in pattern 1010 – misha Jul 17 '19 at 20:47

When you set a signal in Verilog to z, you're allowing some external device to drive it high or low. In the physical implementation, if there isn't any actual device driving the net, then you're allowing random static electricity to drive it to either 0 or 1. You shouldn't expect to see an actual "Z" state in the physical circuit.
• In hardware, dataread will never be z. You should read about the memory behavior in the Altera documentation. But there isn't even a read_enable input to the memory, so it will likely just output the value from whatever address it is given, even if you're also doing a write at the same time. You need to keep track in your own logic when the address given is something you want to read, and only act on the output of the memory when it makes sense to do so. – The Photon Jul 17 '19 at 21:14