# Fastest LCD data throughput 8080 or SPI

I recently ordered a 128x128 graphic black/white display with a ST7541 chip-on-glass. It took me 2,5 days debugging and frustration to discover that they didn't wire SPI through the flatcable.

A big trap for beginners, when you use the datasheet of the ST7541 chip as a reference while coding.

So I rewrote my driver to parallel driving mode and everything is up and running now.

This got me thinking what would be the best option performance wise to continue my product development. SPI or 8080 interfacing?

I drive the display with an Atmega329 and we have enough pins to do 8080. First I thought 8080 would be the fastest, but I'm not sure if PORTD = displaybyte is a very fast and optimized way of putting so much data through.

I guess the SPI architecture and MOSI pin is designed for higher data throughput? Or are they basically behave exact the same way?

The raw speed of the physical interface doesn't really matter all that much, because the effective throughput is going to be limited by the BUSY status controlled by the display anyway. It's probably safe to assume that all of the interface options are capable of keeping the display "busy" most of the time.

The minimum cycle time of the 8080 interface is given on page 61 of the datasheet: 240 ns @ 3.3V. It's the same for the 6800 interface, too.

The 3-/4-wire interface clock period is a minimum of 50 ns (page 65), so in terms of byte transfers, it's going to be roughly 60% as fast as the parallel interface (400 ns per byte).

The IIC interface is limited to a clock frequency of 400 kHz (2.5 µs per bit, 22.5 µs per byte), so this is the slowest option of all.

• I would tend to disagree. From my experience, viewing experience will depend on how quickly an entire screen worth of bits can be written to the display. Jul 18 '19 at 12:26
• @uglyoldbob: The difference between parallel and SPI is just not that significant. Jul 18 '19 at 12:42
• On an Atmega329, I suspect that the SPI hardware module might out-perform a bit-banged parallel port interface. I doubt that it would be possible to get very close to a 240ns byte cycle time. Jul 18 '19 at 12:53
• thanks so much for helping me out Jul 18 '19 at 12:58
• @brhans: At 16 MHz, a 4-instruction sequence requires 250 ns, which is pretty close. I suspect that you need at least 4 instructions to either bit-bang the parallel interface or to service the SPI peripheral, so again, it's a wash either way. Also, the SPI can only operate at 8 MHz max (125 ns/bit, 1 us/byte) anyway. Jul 18 '19 at 13:07