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I am working on synthesizing generated ATPG test vectors and implementing them on an FPGA. However, there's plenty of "don't care" values 'X' in the stimuli and response vectors.

I am not sure how the synthesizer will treat the 'X' values, which will make test vectors comparison to fail. Is there a technique on how to implement test vectors with plenty of 'X' values?

I am coding in Verilog, my vector length is around 1911 bit with more than 200 vectors to be tested.

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  • \$\begingroup\$ What do you mean by "synthesizing...test vectors"? You don't synthesize the test vectors, you simulate them or apply them with a real hardware tester. How/why are you "implementing" test vectors on an FPGA? \$\endgroup\$ – Elliot Alderson Jul 18 at 20:26
  • \$\begingroup\$ I have already simulated the Test Vectors Now I have to inject them , by synthesizing I mean I will use an FPGA to inject those test vectors to the actual chip. I have already done a similar task before, vectors were deterministic. \$\endgroup\$ – Hachani Ahmed Jul 18 at 22:40
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What you ask for makes no sense: A test vector is an actual signal. A signal doesn't take the value "don't care"; it takes one of two states.

It might not be in a well-defined state, but you can't produce "not well-defined" as state.

You probably just want to try a random subsampling of setting the Xs to either 0 or 1.

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  • \$\begingroup\$ those test vectors are generated automatically, by Modus (a cadence software) in order to test a chip , \$\endgroup\$ – Hachani Ahmed Jul 18 at 19:58
  • \$\begingroup\$ Well, the response part of a test vector can have "don't care" values. I don't understand what you mean by "try a random subsampling"...the OP wants to synthesize the vectors...which also makes no sense, but there it is. \$\endgroup\$ – Elliot Alderson Jul 18 at 20:28
  • \$\begingroup\$ @ElliotAlderson I meant that if he needs to test with a (simulated) signal that contains undefined states, the way to do that would by simulate with a few of these states swapped between runs and ensure the result doesn't care about that. \$\endgroup\$ – Marcus Müller Jul 18 at 20:39
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You can replace the X values in the stimulus with 0 (or 1, you can decide). Then run a simulation of the DUT design using these modified test vectors. Record the actual response of the DUT as the new response part of the vector. So now you have a modified set of vectors, where the Xs in the stimulus have been replace with an aribtrary 0 or 1 value, and the Xs in the response have been replaced with the logic value that should actually appear on the output signals.

If you still have Xs in the response then you need to think long and hard about why they are there. If you can convince yourself that these bits in the response really are "don't care" outputs then you will need to use two bits in the test vector for each of these output signals...one bit will indicate whether the output signal is to be ignored, and the other bit will indicate what the signal's value should be if it is not ignored.

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  • \$\begingroup\$ I have already Replaced the X values in the stimulus, and I still have Xs in the Record. I will try to see if I can get a deterministic response . \$\endgroup\$ – Hachani Ahmed Jul 19 at 12:15

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