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I was finding test points in a schematic of an Analog Devices Evaluation board. In one of the schematic pages, there is a clause mentioned "do not populate test points".

Does anyone knows what it means ?

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Yes, it means they are points provided for testing purposes so do not connect components etc to those points.

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    \$\begingroup\$ Additionally, it is an easy way to exclude a component from BOM (as TP have reference designators) , some EDA have special component type for test points that do not require this work around, but even then Often a PCB assembly house will inquire about missing designators between CAD data and the BOM . so an explicit DNP is a normal engineering style to address this when there is a production requirement to check BOM and CAD for consistency. \$\endgroup\$ – crasic Jul 19 at 1:44
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Test points are very useful during development. A test point can be a flat SMT pad, or a throughole pad. Sometimes, a test point has a loop for clipping a probe onto (throughole examples, SMT examples). Sometimes, these loops are used only during R&D testing. In mass production the test points are contacted by automated test equipment, and the loops aren't installed in production to save cost.

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    \$\begingroup\$ I love test points, having worked on boards without them for a year. \$\endgroup\$ – DKNguyen Jul 19 at 15:49
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    \$\begingroup\$ @DKNguyen For sanity's sake, at least a ground testpoint for a scope probe, please. \$\endgroup\$ – Spehro Pefhany Jul 19 at 15:50

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