# Number guessing game:Compare numbers and position in Verilog

I'm designing the number guessing game,aka mastermind,1A2B,And I'm stuck. I'm having problem with how to compare the 2 set of 4-digit numbers and output ? A ? B.

? A : when the number's position and value is correct,increase A's value,like,

1234=1234 => 4A0B,1234=1235 => 3A0B ...etc.


? B : when the numbers value is correct but position is not correct,increase B's value,like

1234=4321 =>0A4B,1234=7843 => 0A2B, 1234=5321 =>0A3B...etc.


Initially I'm thinking to compare both of them by each digit,but then when I use if-else if-else statement to describe it,no matter how I code it,it'll only compare 1 digit,even though I wrote it to compare 2-digit at once...

My biggest question is,how to compare these 2 set of 4-digit numbers and judge its position and value,then output how many A's how many B's.

Codes based on my thoughts and only able to compare 1-digit at a time,even though,I tried code it to compare 2-digit at a time...ultimate goal is to compare 2-set of 4-digit.

Disp_Save is register for saved answer ;

Segs_R is register for input display 7seg on the right-hand side.

Segs_L is register for compared result displaying 7seg on the left-hand side,default displaying 0A0b.

Css is Choosing States,in this case,Css<=0; is return to Keypad detecting state.

           if(Disp_Save[3:0]==Segs_R[3:0])
begin
Segs_L<=16'h1A0b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[3:0]==Segs_R[7:4])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[3:0]==Segs_R[11:8])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[3:0]==Segs_R[15:12])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[7:4]==Segs_R[7:4])
begin
Segs_L<=16'h1A0b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[7:4]==Segs_R[3:0])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[7:4]==Segs_R[11:8])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[7:4]==Segs_R[15:12])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[11:8]==Segs_R[11:8])
begin
Segs_L<=16'h1A0b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[11:8]==Segs_R[3:0])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[11:8]==Segs_R[7:4])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[11:8]==Segs_R[15:12])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[15:12]==Segs_R[15:12])
begin
Segs_L<=16'h1A0b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[15:12]==Segs_R[3:0])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[15:12]==Segs_R[7:4])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[15:12]==Segs_R[11:8])
begin
Segs_L<=16'h0A1b;
Segs_R<=16'h0;
Css<=0;
end

else if(Disp_Save[3:0]==Segs_R[3:0] && Disp_Save[7:4]==Segs_R[7:4])
begin
Segs_L<=16'h2A0b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[7:4]==Segs_R[3:0] && Disp_Save[3:0]==Segs_R[7:4])
begin
Segs_L<=16'h0A2b;
Segs_R<=16'h0;
Css<=0;
end
else if(Disp_Save[3:0]==Segs_R[11:8] && Disp_Save[7:4]==Segs_R[15:12])
begin
Segs_L<=16'h0A2b;
Segs_R<=16'h0;
Css<=0;
end

else
begin
Segs_L<=16'h0A0b;
Segs_R<=16'h0;
Css<=0;
end


This isn't a full answer since it is homework. Basically, for each of the four input pairs, you will need an A output and a B output. They need to be four separate bits each. Then for the final output you need to add up the number of A's and the number of B's. I don't see any addition in your code yet, and it looks like all of the comparisons are changing a single result instead of four separate results.

A bit more detail trying to clear up some confusion. Here is some pseudo-code showing the basic structure:

// digit 0
if (input_0 == goal_0)
A0 = 1
B0 = 0
else
A0 = 0
if (input_0 == goal_1 or input_0 == goal_2 or input_0 == goal_3)
B0 = 1
else
B0 = 0

// digit 1
if (input_1 == goal_1)
A1 = 1
B1 = 0
else
A1 = 0
if (input_1 == goal_0 or input_1 == goal_2 or input_1 == goal_3)
B1 = 1
else
B1 = 0

// ...
// similarly for digits 2 and 3


• Well,yeah,it's from the summer VLSI design course...I'm considering use 4-bit comparator,but I don't understand why it needs to be added,won't it change comparing value?and so for 4-digit input,I'll need to separate each for 4 bits and A's output,B's output,lite Segs_R[15:0] = Segs[3:0] , Segs[7:4],Segs[11:8],Segs[15:12] and each of them have to have A's output and B's output??? I'm even more confused... Commented Jul 19, 2019 at 14:37