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I have an entity dummy with an input port signal of type std_logic_vector:

entity dummy is
    generic (
        LENGTH : natural);
    port (
        A : in std_logic_vector (LENGTH - 1 downto 0);
        Q : out std_logic);
end entity;

When instantiating dummy, is it allowed to associate A with (others => x), where x is a signal of type std_logic?

dummy_i: entity work.dummy
    generic map (
        LENGTH => 4)
    port map (
        A => (others => x),
        Q => open);

ModelSim 10.7b stops with the error message

** Fatal: (vsim-3420) Array lengths do not match. Left is 4 (3 downto 0). Right is 0 (-1 downto 0 (null array))

It works, however, if

  • I use (others => '0') instead of (others => x) (replace #1a with #1b), or
  • the length of port signal A of entity dummy does not depend on the generic (replace #2a with #2b).

Full MWE:

library ieee;
use ieee.std_logic_1164.all;

entity dummy is
    generic (
        LENGTH : natural);
    port (
        A : in std_logic_vector (LENGTH - 1 downto 0); -- #2a
        --A : in std_logic_vector (3 downto 0); -- #2b
        Q : out std_logic);
end entity;

architecture rtl of dummy is
begin
    Q <= '0';
end architecture;


library ieee;
use ieee.std_logic_1164.all;

entity modelsim_others_bug_testbench is
end modelsim_others_bug_testbench;

architecture rtl of modelsim_others_bug_testbench is 
    signal x : std_logic;
begin
    x <= '0';

    dummy_i: entity work.dummy
        generic map (
            LENGTH => 4)
        port map (
            A => (others => x), -- #1a
            --A => (others => '0'), -- #1b
            Q => open);
end architecture;
```
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9
  • \$\begingroup\$ Heh, that's interesting, I can get it working by defining a new type that's an array of std_logic \$\endgroup\$
    – DonFusili
    Jul 19, 2019 at 14:09
  • \$\begingroup\$ What you have done is not legal. What exactly do you want to achieve? Remember that VHDL is strongly typed and std_logic is different type than std_logic_vector even if the length of the vector is 1 (0 downto 0). \$\endgroup\$
    – Al Bundy
    Jul 19, 2019 at 15:53
  • \$\begingroup\$ @AlBundy note that I'm not assigning x but (others => x). I want all elements of that vector to be x. \$\endgroup\$
    – Martin
    Jul 19, 2019 at 16:40
  • \$\begingroup\$ I've edited the question to LENGTH => 4 instead of LENGTH => 1 to emphasize that A is indeed intended as a vector. \$\endgroup\$
    – Martin
    Jul 19, 2019 at 16:42
  • \$\begingroup\$ I bet this is going to end up being a problem with when genetics are evaluated. Try to assign a std_logic_vector outside the port map using (others => x). Then you can assign said vector to A in the port map. \$\endgroup\$
    – user110971
    Jul 19, 2019 at 17:35

1 Answer 1

0
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Prior to VHDL-2008: You cannot perform such action : A => (others => x) because this line is seen as an operation and that is not possible in an instantiation.

(like in this post for example: Warning : Actual for formal port a is neither a static name nor a globally static expression)

However, there is a way to work around that, you have to create a new signal y :

library ieee;
use ieee.std_logic_1164.all;

entity dummy is
    generic (
        LENGTH : natural);
    port (
        --A : in std_logic_vector (LENGTH - 1 downto 0); -- #2a
        A : in std_logic_vector (3 downto 0); -- #2b
        Q : out std_logic);
end entity;

architecture rtl of dummy is
begin
    Q <= '0';
end architecture;


library ieee;
use ieee.std_logic_1164.all;

entity modelsim_others_bug_testbench is
end modelsim_others_bug_testbench;

architecture rtl of modelsim_others_bug_testbench is 
    signal   x  : std_logic;
    signal   y  : std_logic_vector(3 downto 0); --New signals
begin

    x <= '1';
    y <= (others => x);

    dummy_i: entity work.dummy(rtl)
        generic map (
            LENGTH => 4)
        port map (
            --A => (others => x),   -- #1a Does not work
            --A => (others => '0'), -- #1b Works
            A => y,                 -- #1c Works
            Q => open);

end architecture;

Notice that when copy/pasting your code on Vivado, the error is: Actual for formal port a is neither a static name nor a globally static expression

I let you modify your code so that you can use the generic LENGTH.

With VHDL-2008:

If look in the norm: http://www.fis.agh.edu.pl/~skoczen/hdl/ieee_std/ieee1076-2008.pdf You can find on paragraph 6.5.6.3 Port clauses:

If a formal port of mode in is associated with an expression that is not globally static (see 9.4.1) and the formal is of an unconstrained or partially constrained composite type requiring determination of index ranges from the actual according to the rules of 5.3.2.2, then the expression shall be one of the following:

  • The name of an object whose subtype is globally static

  • An indexed name whose prefix is one of the members of this list

  • A slice name whose prefix is one of the members of this list and whose discrete range is a globally static discrete range

  • An aggregate, provided all choices are locally static and all expressions in element associations are expressions described in this list

  • A function call whose return type mark denotes a globally static subtype

  • A qualified expression or type conversion whose type mark denotes a globally static subtype

  • An expression described in this list and enclosed in parentheses

In other word, in VHDL-2008, the code you provided works (I have no error using it with Vivado 2018.1, simulation works as expected)

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