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I have been looking more into how CPU's work, and have a question. If I have a instruction that e.g. takes a 64bit address and a register, and copies the value from that address into the register. And that instruction has a 2 byte opcode. Then let's say the entire instruction is 80 bits in size.(8 bytes) Then how would it execute that instruction? Since I presume it doesn't fit in the instruction register(because the register is 64 bits). Does it just take the opcode and fetch the address(and later it's value) and register later? Or does it have multiple registers? Or does it have one mega big instruction register to fit it all?

Thanks!

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  • \$\begingroup\$ I used to work at Intel doing chipset testing. The Intel architecture used a 32-byte internal buffer and provided sufficient logic to parse up to three simple instructions per clock from that buffer. (It could only handle one complex instruction per clock, though.) These were translated into the ROB (re-order buffer) which is really just a set of RISC instructions that implement the x86 instructions, while also allowing for out of order execution. The "retire-unit" completes the process by making sure that it retires RISC instructions in the ROB, "in-order." \$\endgroup\$ – jonk Jul 19 at 21:54
  • \$\begingroup\$ @jonk So 32 bytes for the instruction. But how does it parse the instruction? Does it just take the instruction, and use some microcode table to find what microinstructions need to be done or is it more complicated? Also, am I correct that these "RISC instructions that implement x86 instructions" are the microinstructions I am talking about? Thanks! \$\endgroup\$ – appmaker1358 Jul 20 at 13:24
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Being a 64-bit architecture does not mean there is a single 64-bit instruction register where everything must fit. X86_64 instructions can be up to 15 bytes in length. Each opcode is decoded for execution. In your example, there would be an opcode for moving data that needs another opcode byte to know what to do, and then it knows that 64-bit immediate address follows that must be read and which register will be the target.

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  • \$\begingroup\$ In fact, there are valid combination of instruction prefixes and suffixes which can be used to make a meaningful x86_64 instruction more than 15 bytes in length. However these are by definition illegal, as the processor forbids instructions > 15 bytes, I guess in order to simplify instruction decoders. \$\endgroup\$ – anrieff Jul 19 at 20:00
  • \$\begingroup\$ Indeed the theorethical answer might be infinite. However existing processors have a limit after which they throw an exception. \$\endgroup\$ – Justme Jul 19 at 21:20
  • \$\begingroup\$ I don't really understand. Why does it need/have 2 opcodes? And if it knows the next 64 bits are the address, how does it read it? Does it fetch it from ram/cache, or did it store it in some register before hand? \$\endgroup\$ – appmaker1358 Jul 19 at 21:23
  • \$\begingroup\$ Well you said it has two bytes. I did not look for the opcode map how this kind of operation can be encoded. If it does take two bytes then clearly it can't fit in one byte. First byte tells it is a move operation but the second tells what kind of move operation specifically. Internally who knows how it is stored, but simply the program counter tells where to fetch the instruction and the decoder then looks at the bytes and knows it must read memory defined by the immediate address at PC+2 and store it to a register defined by the opcode. That is what a human armed with an opcode map would do. \$\endgroup\$ – Justme Jul 19 at 21:37
  • \$\begingroup\$ Ah, you meant it that way. I thought of some thing else. I originally meant these 2 bytes as one opcode, but your way seems better. Am I correct that the "decoder" actually executes the instruction, so: The instruction is loaded, then the "decoder" looks at it and does what it is programmed to do for that instruction, e.g. fetch the value from an address, and then copy it into a registor.(Like described in my initial post)? \$\endgroup\$ – appmaker1358 Jul 20 at 13:28
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X86 supports variable length instructions, so the "instruction register" isn't very simple or limited to 64 bits. The CPU has a rather complex parser that determines the length of the instructions and can extract multiple sequential instructions at the same time.

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  • \$\begingroup\$ How does this parser work? Is there a site where I can read up on it? \$\endgroup\$ – appmaker1358 Jul 19 at 21:21
  • \$\begingroup\$ @appmaker1358 Not really; it's proprietary to Intel (or AMD). You can imagine a few ways it could possibly work though. It may interest you to know that data comes in from the data cache 512 bits at a time - not sure how much data comes from the instruction cache at a time, but I'd guess 256 or 512 bits. \$\endgroup\$ – immibis Jul 22 at 3:56

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