I can easily understand how .bss and the code have physical representations in the processor which has a memory bank for the instructions that a program counter can count up and the bss (block starting symbol) is just global data. But then there is the stack for local variables and the heap for dynamic memory. How are these things put on the circuit physically?


Note: I refer mostly to x86 as I'm most familiar with it and it's widely documented:

On x86 (and most other architectures) the stack is just resident in memory like everything else. The processor manipulates the stack through a pointer, which is usually stored in a register (the stack pointer). Push and pop instructions will change the value of the stack pointer, changing where the top of the stack is.

The heap is a software abstraction. Like the name implies, it's just a lump of RAM which an allocator slices up and hands out pointers to. In physical terms, the heap doesn't look any different to any other part of RAM.

Paging and segmentation are tangentially related to the heap, however. They're mostly to do with multi-tasking, where processes can't be allowed to modify RAM they don't explicitly own.

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    \$\begingroup\$ Paging is more about memory management in general - the unit at which physical memory is mapped to a logical address - than just access restrictions, though the later tend to be applied as an additional feature of the memory management unit. \$\endgroup\$ – Chris Stratton Oct 18 '12 at 13:58

Logically speaking the stack, and heap are usually just memory; at an implementation level though, they will hopefully be served primarily from cache. In most systems they get there dynamically via caching algorithms, but there have been systems which support explicit location in cache or other faster-than-usual memory, and likely also those which support leaving hints that particular data should have preferential priority for placement there as space permits.

Design of low level software and compiler code generators hopefully takes into account organization of data access which is likely to result in good cache utilization, vs. constant cache misses.

Some processors have a return address register, which functions as a sort of one-deep explicit stack cache (there are probably those with several deep hardware stacks too, though examples don't come to mind).


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