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I'm a newbie at designing at the nanopower level, hence my question. In this circuit, I have plastic fiber optical inbound signal that drives D1 photodiode, whose dark current is extremely low (tens of nanoamps). It will be an RS-485 like signal up to 56Kb maximum.

With no fiber optic signal, I need the quiesce current of all components to be as low as possible to maximize battery life. The N-Channel enhanced mode MOSFET BSS138 is used as a switch to drive two outputs: 1) a fiber optic LED used as a repeater, and 2) a UART RxData and external interrupt line into a PIC16LF MCU. R10 was chosen as a Very Weak Pull-up to minimize quiescent current at around 600 nA.

Plastic Fiber Optic Interface to PIC MCU

I'm also unsure if my attempts to use the single BSS138 for dual purposes like this is going to work. The MCU UART needs a high signal (RS-232 mark) with no optic signal present. The IF-E96E datasheet suggests it requires many mAs to conduct, so unsure how that's going to factor in.

So, am I on the right track here or heading into the ditch? If it's the ditch, how can I keep component costs and quiescent power at a minimum here?

In particular, when JP2 is not installed, taking the photo LED out of the circuit, will 600 nA be enough current to create flow and voltage drop across the BSS138? How low can I realistically go with R10 and still expect reliable operation?

Many thanks. Rick

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    \$\begingroup\$ As with all CMOS logic, the goal to minimize power is to minimize switched FET capacitance while reducing RdsOn to meet the required rise time. T=Ron*C. This is the criteria I would use. \$\endgroup\$
    – Tony Stewart EE75
    Jul 23, 2019 at 0:21
  • \$\begingroup\$ So add up all the known component capacitance plus estimated stray PCB capacitance? \$\endgroup\$
    – rbraddy
    Jul 23, 2019 at 0:28
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    \$\begingroup\$ Yes. The bigger the FET and LED, the more capacitance but also lower resistance. Cable capacitance is 60 to 100pF/m depending on turns and gap. \$\endgroup\$
    – Tony Stewart EE75
    Jul 23, 2019 at 0:54
  • \$\begingroup\$ Okay. So BSS138 output capacitance is 13 pF, add 2 pF of stray capacitance for 15 pF, then at 4.7M ohms the RC Time constant is about 70 uS, or just 14.2 KHz. That would then limit baud rate to 9600 or maybe 14.4 Kb. Hmmm. But when the photo LED is used, baud rate ceiling is much higher due to lower resistance and faster rise times. This certainly helps set some boundaries. \$\endgroup\$
    – rbraddy
    Jul 23, 2019 at 0:59
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    \$\begingroup\$ Do you have a good reason to expect the offset voltage of the TS881 will always be negative? If you have positive offset voltage, the output of U4 will always be high. \$\endgroup\$
    – The Photon
    Jul 23, 2019 at 1:22

1 Answer 1

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Thank you all for your feedback and comments, which have enabled me to (hopefully) evolve the design to address its shortfalls yet meet the nanopower quiescent current goal.

enter image description here

The revised design uses a voltage divider reference for the comparator to address potential issues around noise and the comparator's on/off thresholds, while keeping steady voltage divider current at a bare minimum. The smaller 22K R10 resolves the time constant issue with FET output capacitance and the target baud rate when JP2 is disconnected. The final comparator voltage divider may require some minor tweaking but I'm now in the ballpark with the design.

Very helpful! Much appreciated.

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