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A Qsys system has to be generated to create all the source files for simulation and synthesis. Here it shall create copies of the primary RTL source files of custom components also.

These copies shall exist inside the simulation and synthesis folders inside the Qsys system directory, I never figured out why it has to create local copies.

If I am running a simulation, I would tend to modify the RTL file continuously, recompile it and rerun the simulation. This is just how development and debugging is done in general.

However, how will it work with Qsys? Do I really have to regenerate the Qsys system every time, so the source file in the simulation folder is updated before I restart and rerun the simulation?

Do I misunderstand how Qsys custom component verification is to be carried out?

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  • \$\begingroup\$ Is this when you are debugging your own RTL that interfaces with the QSys blocks or when you are debugging the generated QSys blocks to see if you got the parameters correctly? \$\endgroup\$ – DonFusili Jul 23 at 16:18
  • \$\begingroup\$ Just edit the file in the simulation folder and then copy it back to your IP directory when done. \$\endgroup\$ – Tom Carpenter Jul 23 at 16:36
  • \$\begingroup\$ DonFusili, this is when debugging my own RTL to verify that it does the right things in the Qsys system. This basically involves verifying that the Avalon-MM interfaces correctly latch input and write output. \$\endgroup\$ – Quantum0xE7 Jul 24 at 6:35
  • \$\begingroup\$ Do you script your synthesis runs? \$\endgroup\$ – DonFusili Jul 24 at 6:49
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Just edit the file in the simulation folder and then copy it back to your IP directory when done.

If you use some form of version control such as git you can keep track of the changes you make in the simulation folder and make sure that you have copied them back.

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  • \$\begingroup\$ Is this really the proper way to do it? Is this how you have done it? I am going to start work on custom component today so this question came in my mind. I am not sure about the different ways to deal with it. \$\endgroup\$ – Quantum0xE7 Jul 24 at 6:34
  • \$\begingroup\$ @Quantum0xE7 it's how I've been doing it for 5 years or so. You'll find that Qsys/Platform Designer is a hodgepodge of bugs and annoyances, which frequently does things that make no sense (pointlessly generating block symbol files in random folders every time you save for example). My advice is to use it sparingly - build small subsystems that you connect in HDL. \$\endgroup\$ – Tom Carpenter Jul 24 at 8:10
  • \$\begingroup\$ For Avalon-MM, you might find this template useful. \$\endgroup\$ – Tom Carpenter Jul 24 at 8:12

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